ABSTRACT: 3D integration is expected to lead to a semiconductor industry paradigm shift due to its tremendous benefits to performance, data bandwidth, functionality, heterogeneous integration, power and cost. In this work, we consider the case where solder balls and through-strata-vias (TSVs) are paired to electrically connect stacked chips in a vertical fashion. For the given solder-TSV configurations, transient analysis (e.g. the 3D bathtub contour) shows a good behavior of solder-TSV signal integrity in the time domain. With regard to the frequency response from 1 MHz to 10 GHz, the performances are compared among different solder-TSV configurations. Solders with diameters of 25 - 100 μm have negligible losses in their electrical performance. The gain along the signal path is reduced with the increasing number of stacked strata and eye diagrams get distorted correspondingly. As the site offset between solders and TSVs becomes large, the signal loss is exacerbated due to the loss from the needed redistribution layer (RDL). In the solder-TSV chain structure, the electrical characteristics also deteriorate with long RDLs. Two different solder-TSV arrays give very similar near-end crosstalk (NEXT) and far-end crosstalk (FEXT). In addition, the return loss, insertion loss, NEXT and FEXT of a rhombus solder-TSV array are accurately modeled by a SPICE netlist. The circuit results show very small fitting errors for the magnitude and phase of elements in the scattering matrix. This modeling approach enables 3D architecture evaluation and design using current 2D CAD tools.
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conference on; 11/2010