K. Rose

Rensselaer Polytechnic Institute, Троя, New York, United States

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Publications (29)5.98 Total impact

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    ABSTRACT: Decoupling capacitors are essential to reduce high transient current noise and to provide a low impedance power delivery path. 3D technology has several advantages for power delivery, and this work investigates the impacts of decoupling capacitors on through-silicon-via (TSV)-based 3D power networks using a novel hybrid modeling approach, i.e., combining electromagnetic (EM) and SPICE simulations. We first partitioned a 3D system into a number of components, extracted the RLGC parasitics for each decomposed physical element, and imported them into an assembled system-level equivalent circuit. Through comparing and analyzing the effectiveness of several decoupling strategies, design tradeoffs are made in selecting the proper values and placement of decoupling capacitors to ensure optimal power distribution solution in 3D architectures.
    01/2012; DOI:10.1109/ASMC.2012.6212938
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    ABSTRACT: It is important to understand how to deliver power into 3D heterogeneous systems, which require different power supplies for different components (e.g., digital, analog, mixed-signal, MEMS parts). This paper reports on a study for a simplified case, where the two power supplies with different voltage levels are uniformly distributed through a TSV-based 3D system. In addition to intrinsic voltage losses along the interconnections, we investigated for the first time the power noises due to electrical couplings between the multiple power supplies. We evaluated the through-silicon-via (TSV)-based 3D power delivery networks by combining the electromagnetic (EM) and SPICE simulations. With this hybrid approach, we first partitioned the 3D system into a number of elements, extracted the RLGC parasitics for each decomposed physical element, and imported them into an assembled system-level equivalent circuit to characterize the 3D power distribution networks.
    Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd; 01/2012
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    ABSTRACT: While three-dimensional (3D) technology has several advantages for power delivery, an integrated chip-level, interposer-level, and package-level power distribution network in through-silicon-via (TSV)-based 3D system has to be modeled and evaluated. This paper reports on modeling of power delivery into 3D chip stacks on a silicon interposer/packaging substrate using a novel hybrid approach, i.e., combining the electromagnetic (EM) and analytic simulations. We intentionally partition the real stack-up structure of a 3D power network into separate components, i.e., package vias and traces, C-4 solders, interposer TSVs and planar wires, μ-C4 solders, chip TSVs, and on-chip power grids with node capacitors, decoupling capacitors and active current loads. All the passive RLGCs for each component are extracted using an EM simulation tool at a given working frequency point. We then assemble all the components back into a corresponding equivalent circuit model with those EM extracted RLGC values, thus to analyze the supply voltage (Vdd)variation over time for 3D systems in a manner of maximum accuracy and efficiency.
    Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd; 01/2012
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    ABSTRACT: Through-strata-via (TSV) is regarded as a critical component in 3D integration that extends Moore's Law. This paper reports on TSV crosstalk performance under high speed operations using a 3D electromagnetic field solver and a SPICE simulator in both the frequency domain and time domain. Impacts of the rise time, the TSV pitch/height, the substrate resistivity and the guarding TSV termination on crosstalk noise are studied. Effects of adjacent aggressors and their switching patterns on time delay and peak noise of the victim TSV signal are evaluated. For large and dense TSV networks, crosstalk matrices of different TSV line/array arrangements are investigated at certain frequency points, detailing the coupling noise levels among these TSVs. Furthermore, the frequency dependent near-end crosstalk (NEXT) and far-end crosstalk (FEXT) are accurately modeled by SPICE tools.
    3D Systems Integration Conference (3DIC), 2010 IEEE International; 12/2010
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    ABSTRACT: 3D integration is expected to lead to a semiconductor industry paradigm shift due to its tremendous benefits to performance, data bandwidth, functionality, heterogeneous integration, power and cost. In this work, we consider the case where solder balls and through-strata-vias (TSVs) are paired to electrically connect stacked chips in a vertical fashion. For the given solder-TSV configurations, transient analysis (e.g. the 3D bathtub contour) shows a good behavior of solder-TSV signal integrity in the time domain. With regard to the frequency response from 1 MHz to 10 GHz, the performances are compared among different solder-TSV configurations. Solders with diameters of 25 - 100 μm have negligible losses in their electrical performance. The gain along the signal path is reduced with the increasing number of stacked strata and eye diagrams get distorted correspondingly. As the site offset between solders and TSVs becomes large, the signal loss is exacerbated due to the loss from the needed redistribution layer (RDL). In the solder-TSV chain structure, the electrical characteristics also deteriorate with long RDLs. Two different solder-TSV arrays give very similar near-end crosstalk (NEXT) and far-end crosstalk (FEXT). In addition, the return loss, insertion loss, NEXT and FEXT of a rhombus solder-TSV array are accurately modeled by a SPICE netlist. The circuit results show very small fitting errors for the magnitude and phase of elements in the scattering matrix. This modeling approach enables 3D architecture evaluation and design using current 2D CAD tools.
    Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conference on; 11/2010
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    ABSTRACT: Since the conventional planar ICs encountered many physical, technological and economic bottlenecks, D integration by stacking and connecting function blocks in a vertical fashion is regarded as a viable approach to alleviate such bottlenecks. Through-strata-via (TSV) is one of the most attractive D integration solutions, which offers a massive number of short interconnects, high bandwidth, reduced delay and power consumption, heterogeneous integration, small footprint, improved yield, and reduced volume production cost. This paper reports on electrical characterizations and wideband modeling of typical TSV structures up to 100 GHz. The analysis is conducted in both the time domain and frequency domain, unveiling the impacts of processing materials on TSV electrical performance. The accurate broadband modeling approaches and results facilitate and benefit the infant 3D CAD development.
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    ABSTRACT: From a system architecture perspective, 3D technology can satisfy the high memory bandwidth demands that future multicore/manycore architectures require. This article presents a 3D DRAM architecture design and the potential for using 3D DRAM stacking for both L2 cache and main memory in 3D multicore architecture.
    IEEE Design and Test of Computers 11/2009; DOI:10.1109/MDT.2009.105
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    ABSTRACT: As a promising option to address the memory wall problem, 3D processor-DRAM integration has recently received many attentions. Since DRAM tiers must be stacked between the processor tier and package substrate, we must fabricate a large number of through-DRAM through-silicon vias (TSVs) to connect the processor tier and package for power and I/O signal delivery. Although such through-DRAM TSVs will inevitably interfere with DRAM design and induce non-negligible power consumption overhead, little research has been done to study how to allocate these TSVs on the DRAM tiers and analyze their impacts. To address this open issue, this paper first presents a through-DRAM TSV allocation strategy that fits well to the regular DRAM architecture. To demonstrate this design strategy and evaluate trade-offs involved, we develop a CACTI-based modeling tool to carry out extensive simulations over a wide range of design parameters.
    3D System Integration, 2009. 3DIC 2009. IEEE International Conference on; 10/2009
  • Qi Wu, Jian-Qiang Lu, Kenneth Rose, Tong Zhang
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    ABSTRACT: Three-dimensional (3D) integration of a single high performance microprocessor die and multiple DRAM dies has been considered as a viable option to tackle the looming memory wall problem. Meanwhile, on-chip decoupling capacitors are becoming increasingly important to ensure power delivery integrity, particularly for high-performance integrated circuits. Targeting at 3D processor-DRAM integrated computing systems, this paper proposes to use 3D stacked DRAM dies to provide decoupling capacitors for the processor die. This can well leverage the superior capacitor fabrication ability of DRAM to eliminate the area penalty of decoupling capacitor insertion on the processor die. For its practical implementation, a simple uniform decoupling capacitor network design strategy is presented, and circuit SPICE simulations and computer system simulations are carried out to quantitatively demonstrate the effectiveness and illustrate various design trade-offs.
    Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009; 01/2009
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    ABSTRACT: Motivated by increasingly promising three-dimensional (3D) integration technologies, this paper reports an architecture design of 3D integrated dynamic RAM (DRAM). To accommodate the potentially significant pitch mismatch between DRAM word-line/bit-line and through silicon vias (TSVs) for 3D integration, this paper presents two modestly different coarse-grained inter-sub-array 3D DRAM architecture partitioning strategies. Furthermore, to mitigate the potential yield loss induced by 3D integration, we propose an interdie inter-sub-array redundancy repair approach to improve the memory repair success rate. For the purpose of evaluation, we modified CACTI 5 to support the proposed coarse-grained 3D partitioning strategies. Estimation results show that, for the realization of a 1 Gb DRAM with 8 banks and 256-bit data I/O, such 3D DRAM design strategies can effectively reduce the silicon area, access latency, and energy consumption compared with 3D packaging with wire bonding and conventional 2D design. We further developed a memory redundancy repair simulator to demonstrate the effectiveness of proposed inter-die inter-subarray redundancy repair approach.
    10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA; 01/2009
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    ABSTRACT: Simulator accuracy is an important, but seldom examined, part of study on 3D integration. This paper examines inaccurate technology parameters as a source of error for the CACTI and PRACTICS cache simulation tools. By replacing the default parameters with ones derived from information made available in the literature, CACTI simulation error for the 90 nm Itanium2 L3 cache is eliminated almost entirely. We evaluate the effect of this change in technology parameters on 3D design by comparing simulations that use the default parameter values to those using the newly derived ones.
    IEEE International Conference on 3D System Integration, 3DIC 2009, San Francisco, California, USA, 28-30 September 2009; 01/2009
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    ABSTRACT: This paper discusses through-strata-vias (TSVs) technology and presents modeling results of their electrical performance using Agilent's ADS and Momentum simulator. Since TSV is an essential component in three-dimensional (3D) integration/packaging, it is important to explore and investigate its electrical characteristics. A simple face-to-back TSV is studied in frequency domain and time domain. The impact of physical configurations and materials on TSV electrical characteristics is evaluated. An equivalent circuit model is proposed, and the values of passive elements (resistance, inductance and capacitance) within the model are extracted from full-wave scattering parameters.
    IEEE International Conference on 3D System Integration, 3DIC 2009, San Francisco, California, USA, 28-30 September 2009; 01/2009
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    ABSTRACT: Three-dimensional (3D) integration is an emerging technology, which is expected to lead to an industry paradigm shift due to its tremendous benefits. World-wide academic and industrial research activities currently focus on technology innovations, simulation and design, and product prototypes. Anticipated applications may start from memory, portable device, and high performance computer to high-density multi-functional heterogeneous integration of InfoTech-NanoTech-BioTech systems.
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    ABSTRACT: The design of on-chip error correction systems for multilevel code-storage NOR flash and data-storage NAND flash memories is concerned. The concept of trellis coded modulation (TCM) has been used to design on-chip error correction system for NOR flash. This is motivated by the non-trivial modulation process in multilevel memory storage and the effectiveness of TCM in integrating coding with modulation to provide better performance at relatively short block length. The effectiveness of TCM-based systems, in terms of error-correcting performance, coding redundancy, silicon cost and operational latency, has been successfully demonstrated. Meanwhile, the potential of using strong Bose-Chaudhiri-Hocquenghem (BCH) codes to improve multilevel data-storage NAND flash memory capacity is investigated. Current multilevel flash memories store 2 bits in each cell. Further storage capacity may be achieved by increasing the number of storage levels per cell, which nevertheless will correspondingly degrade the raw storage reliability. It is demonstrated that strong BCH codes can effectively enable the use of a larger number of storage levels per cell and hence improve the effective NAND flash memory storage capacity up to 59.1% without degradation of cell programming time. Furthermore, a scheme to leverage strong BCH codes to improve memory defect tolerance at the cost of increased NAND flash cell programming time is proposed.
    IET Circuits Devices & Systems 07/2007; 1(3-1):241 - 249. DOI:10.1049/iet-cds:20060275
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    ABSTRACT: This work discusses the benefits of a SiGe BiCMOS implementation over a CMOS implementation for pipeline A/Ds. While various circuit blocks in a pipeline A/D can benefit from the higher transconductance (g<sub>m</sub>), higher unity gain frequency (f<sub>T</sub>) and lower noise of SiGe HBTs, this work focuses on the most critical block in a pipeline A/D, the operational transconductance amplifier (OTA). An OTA employing an all NMOS pre-amplifier followed by a cascoded SiGe HBT stage with actively cascoded PMOS loads is designed. A prototype 12-bit pipeline A/D achieves a measured SNDR of 62.6 dB and a SFDR of 73.4 dB at 65 MS/s with a power dissipation of 325 mW and operates from dual 1.8 V and 3.3 V supplies.
    Bipolar/BiCMOS Circuits and Technology Meeting, 2007. BCTM '07. IEEE; 01/2007
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    A. Zeng, K. Rose, R.J. Gutmann
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    ABSTRACT: The desire for large size, high-speed, and low-power on-chip memory necessitates early and accurate estimates of memory performance. A new performance model as well as an early cache design tool and predictor of access and cycle time for cache stack (PRACTICS) has been developed for on-chip static random access memory (SRAM) cache design that includes both delay and dynamic-power models. Efficient models for distributed interconnect delays, verified by Cadence simulations, are introduced, and their necessity is demonstrated. In the delay model, the access time is estimated by decomposing each component into several equivalent lumped resistance-capacitance (RC) circuits and using an appropriate order pi model to approximate the distributed wire delays of each stage. The dynamic-power model calculates the charging power dissipation of the load capacitances using the same equivalent lumped RC circuits. The delay model has been validated with an Intel 18-Mb SRAM at the 180-nm node, achieving accuracy to within 10% of the measured results. The dynamic-power model has been validated with an International Business Machines Corporation (IBM) 18-Mb SRAM at the 180-nm node, to within 13% of the measured power consumption. Detailed comparisons between PRACTICS and cache access and cycle time model (CACTI) in both validation cases indicate that an improved wire delay, appropriate circuit structures, and technology dependent parameters are necessary to accurately predict large cache memory performance at deep submicrometer technology nodes. PRACTICS is used to analyze the access time and power consumption in terms of cache sizes and various degrees of associativity for architectural studies. In addition, the PRACTICS simulation results show that repeater insertion reduces the access time significantly, with a small overhead in dynamic-power consumption for large size cache design at deep submicrometer technology
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10/2006; DOI:10.1109/TCAD.2005.858346
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    ABSTRACT: The advantages of 3D design can be exploited by reducing the memory access time. In this article, the authors use a simulator based on analytical models to build an optimal processor-memory configuration for two designs: a graphics processor and a microprocessor. One emerging alternative approach to relieving these interconnect constraints is the use of wafer-level 3D integration, which provides a high density of high-performance, low-parasitic vertical interconnects. A wafer-level 3D design is partitionable into multiple chips connected by short vertical vias. This arrangement reduces the length of many global interconnects without introducing any logic complexity. Wafer-level 3D integration also reduces the required number of repeaters, thereby improving the area efficiency and reducing the power consumed within the interconnect network. With micron-size interwafer vias, wafer-level 3D integration allows a large memory bandwidth with little wafer area consumption. We have developed a software program that allows a first-order comparison of cache designs in 2D and 3D IC technologies. We present a first-order estimate of the performance improvements achieved by 3D implementation of cache memory, with emphasis on large caches in deep-submicron technologies.
    IEEE Design and Test of Computers 12/2005; DOI:10.1109/MDT.2005.138
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    ABSTRACT: A three-dimensional (3D) IC technology platform for high-performance, heterogeneous integration of silicon ICs for mm-wave smart antenna transceivers is presented. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. A low noise amplifier (LNA), power amplifier (PA), and an analog-to-digital converter (ADC) are designed in RF-enhanced SiGe BiCMOS process to operate in the 24 GHz ISM band These critical design blocks serve as a step towards the realization of a complete system integrated with I/O matching networks, switches, antennas, and digital processing in a 3D configuration
    Wireless and Microwave Technology, 2005. WAMICON 2005. The 2005 IEEE Annual Conference; 05/2005
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    ABSTRACT: Not Available
    Wireless and Microwave Technology, 2005. WAMICON 2005. The 2005 IEEE Annual Conference; 02/2005