K. Rose

Xi'an Jiaotong University, Ch’ang-an, Shaanxi, China

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Publications (12)1.62 Total impact

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    ABSTRACT: It is important to understand how to deliver power into 3D heterogeneous systems, which require different power supplies for different components (e.g., digital, analog, mixed-signal, MEMS parts). This paper reports on a study for a simplified case, where the two power supplies with different voltage levels are uniformly distributed through a TSV-based 3D system. In addition to intrinsic voltage losses along the interconnections, we investigated for the first time the power noises due to electrical couplings between the multiple power supplies. We evaluated the through-silicon-via (TSV)-based 3D power delivery networks by combining the electromagnetic (EM) and SPICE simulations. With this hybrid approach, we first partitioned the 3D system into a number of elements, extracted the RLGC parasitics for each decomposed physical element, and imported them into an assembled system-level equivalent circuit to characterize the 3D power distribution networks.
    Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd; 01/2012
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    ABSTRACT: Decoupling capacitors are essential to reduce high transient current noise and to provide a low impedance power delivery path. 3D technology has several advantages for power delivery, and this work investigates the impacts of decoupling capacitors on through-silicon-via (TSV)-based 3D power networks using a novel hybrid modeling approach, i.e., combining electromagnetic (EM) and SPICE simulations. We first partitioned a 3D system into a number of components, extracted the RLGC parasitics for each decomposed physical element, and imported them into an assembled system-level equivalent circuit. Through comparing and analyzing the effectiveness of several decoupling strategies, design tradeoffs are made in selecting the proper values and placement of decoupling capacitors to ensure optimal power distribution solution in 3D architectures.
    01/2012;
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    ABSTRACT: While three-dimensional (3D) technology has several advantages for power delivery, an integrated chip-level, interposer-level, and package-level power distribution network in through-silicon-via (TSV)-based 3D system has to be modeled and evaluated. This paper reports on modeling of power delivery into 3D chip stacks on a silicon interposer/packaging substrate using a novel hybrid approach, i.e., combining the electromagnetic (EM) and analytic simulations. We intentionally partition the real stack-up structure of a 3D power network into separate components, i.e., package vias and traces, C-4 solders, interposer TSVs and planar wires, μ-C4 solders, chip TSVs, and on-chip power grids with node capacitors, decoupling capacitors and active current loads. All the passive RLGCs for each component are extracted using an EM simulation tool at a given working frequency point. We then assemble all the components back into a corresponding equivalent circuit model with those EM extracted RLGC values, thus to analyze the supply voltage (Vdd)variation over time for 3D systems in a manner of maximum accuracy and efficiency.
    Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd; 01/2012
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    ABSTRACT: Through-strata-via (TSV) is regarded as a critical component in 3D integration that extends Moore's Law. This paper reports on TSV crosstalk performance under high speed operations using a 3D electromagnetic field solver and a SPICE simulator in both the frequency domain and time domain. Impacts of the rise time, the TSV pitch/height, the substrate resistivity and the guarding TSV termination on crosstalk noise are studied. Effects of adjacent aggressors and their switching patterns on time delay and peak noise of the victim TSV signal are evaluated. For large and dense TSV networks, crosstalk matrices of different TSV line/array arrangements are investigated at certain frequency points, detailing the coupling noise levels among these TSVs. Furthermore, the frequency dependent near-end crosstalk (NEXT) and far-end crosstalk (FEXT) are accurately modeled by SPICE tools.
    3D Systems Integration Conference (3DIC), 2010 IEEE International; 12/2010
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    ABSTRACT: 3D integration is expected to lead to a semiconductor industry paradigm shift due to its tremendous benefits to performance, data bandwidth, functionality, heterogeneous integration, power and cost. In this work, we consider the case where solder balls and through-strata-vias (TSVs) are paired to electrically connect stacked chips in a vertical fashion. For the given solder-TSV configurations, transient analysis (e.g. the 3D bathtub contour) shows a good behavior of solder-TSV signal integrity in the time domain. With regard to the frequency response from 1 MHz to 10 GHz, the performances are compared among different solder-TSV configurations. Solders with diameters of 25 - 100 μm have negligible losses in their electrical performance. The gain along the signal path is reduced with the increasing number of stacked strata and eye diagrams get distorted correspondingly. As the site offset between solders and TSVs becomes large, the signal loss is exacerbated due to the loss from the needed redistribution layer (RDL). In the solder-TSV chain structure, the electrical characteristics also deteriorate with long RDLs. Two different solder-TSV arrays give very similar near-end crosstalk (NEXT) and far-end crosstalk (FEXT). In addition, the return loss, insertion loss, NEXT and FEXT of a rhombus solder-TSV array are accurately modeled by a SPICE netlist. The circuit results show very small fitting errors for the magnitude and phase of elements in the scattering matrix. This modeling approach enables 3D architecture evaluation and design using current 2D CAD tools.
    Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conference on; 11/2010
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    ABSTRACT: Since the conventional planar ICs encountered many physical, technological and economic bottlenecks, D integration by stacking and connecting function blocks in a vertical fashion is regarded as a viable approach to alleviate such bottlenecks. Through-strata-via (TSV) is one of the most attractive D integration solutions, which offers a massive number of short interconnects, high bandwidth, reduced delay and power consumption, heterogeneous integration, small footprint, improved yield, and reduced volume production cost. This paper reports on electrical characterizations and wideband modeling of typical TSV structures up to 100 GHz. The analysis is conducted in both the time domain and frequency domain, unveiling the impacts of processing materials on TSV electrical performance. The accurate broadband modeling approaches and results facilitate and benefit the infant 3D CAD development.
    01/2010;
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    ABSTRACT: From a system architecture perspective, 3D technology can satisfy the high memory bandwidth demands that future multicore/manycore architectures require. This article presents a 3D DRAM architecture design and the potential for using 3D DRAM stacking for both L2 cache and main memory in 3D multicore architecture.
    IEEE Design and Test of Computers 11/2009; · 1.62 Impact Factor
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    ABSTRACT: As a promising option to address the memory wall problem, 3D processor-DRAM integration has recently received many attentions. Since DRAM tiers must be stacked between the processor tier and package substrate, we must fabricate a large number of through-DRAM through-silicon vias (TSVs) to connect the processor tier and package for power and I/O signal delivery. Although such through-DRAM TSVs will inevitably interfere with DRAM design and induce non-negligible power consumption overhead, little research has been done to study how to allocate these TSVs on the DRAM tiers and analyze their impacts. To address this open issue, this paper first presents a through-DRAM TSV allocation strategy that fits well to the regular DRAM architecture. To demonstrate this design strategy and evaluate trade-offs involved, we develop a CACTI-based modeling tool to carry out extensive simulations over a wide range of design parameters.
    3D System Integration, 2009. 3DIC 2009. IEEE International Conference on; 10/2009
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    ABSTRACT: Motivated by increasingly promising three-dimensional (3D) integration technologies, this paper reports an architecture design of 3D integrated dynamic RAM (DRAM). To accommodate the potentially significant pitch mismatch between DRAM word-line/bit-line and through silicon vias (TSVs) for 3D integration, this paper presents two modestly different coarse-grained inter-sub-array 3D DRAM architecture partitioning strategies. Furthermore, to mitigate the potential yield loss induced by 3D integration, we propose an interdie inter-sub-array redundancy repair approach to improve the memory repair success rate. For the purpose of evaluation, we modified CACTI 5 to support the proposed coarse-grained 3D partitioning strategies. Estimation results show that, for the realization of a 1 Gb DRAM with 8 banks and 256-bit data I/O, such 3D DRAM design strategies can effectively reduce the silicon area, access latency, and energy consumption compared with 3D packaging with wire bonding and conventional 2D design. We further developed a memory redundancy repair simulator to demonstrate the effectiveness of proposed inter-die inter-subarray redundancy repair approach.
    10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA; 01/2009
  • Qi Wu, Jian-Qiang Lu, Kenneth Rose, Tong Zhang
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    ABSTRACT: Three-dimensional (3D) integration of a single high performance microprocessor die and multiple DRAM dies has been considered as a viable option to tackle the looming memory wall problem. Meanwhile, on-chip decoupling capacitors are becoming increasingly important to ensure power delivery integrity, particularly for high-performance integrated circuits. Targeting at 3D processor-DRAM integrated computing systems, this paper proposes to use 3D stacked DRAM dies to provide decoupling capacitors for the processor die. This can well leverage the superior capacitor fabrication ability of DRAM to eliminate the area penalty of decoupling capacitor insertion on the processor die. For its practical implementation, a simple uniform decoupling capacitor network design strategy is presented, and circuit SPICE simulations and computer system simulations are carried out to quantitatively demonstrate the effectiveness and illustrate various design trade-offs.
    Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009; 01/2009
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    ABSTRACT: This paper discusses through-strata-vias (TSVs) technology and presents modeling results of their electrical performance using Agilent's ADS and Momentum simulator. Since TSV is an essential component in three-dimensional (3D) integration/packaging, it is important to explore and investigate its electrical characteristics. A simple face-to-back TSV is studied in frequency domain and time domain. The impact of physical configurations and materials on TSV electrical characteristics is evaluated. An equivalent circuit model is proposed, and the values of passive elements (resistance, inductance and capacitance) within the model are extracted from full-wave scattering parameters.
    IEEE International Conference on 3D System Integration, 3DIC 2009, San Francisco, California, USA, 28-30 September 2009; 01/2009
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    ABSTRACT: Simulator accuracy is an important, but seldom examined, part of study on 3D integration. This paper examines inaccurate technology parameters as a source of error for the CACTI and PRACTICS cache simulation tools. By replacing the default parameters with ones derived from information made available in the literature, CACTI simulation error for the 90 nm Itanium2 L3 cache is eliminated almost entirely. We evaluate the effect of this change in technology parameters on 3D design by comparing simulations that use the default parameter values to those using the newly derived ones.
    IEEE International Conference on 3D System Integration, 3DIC 2009, San Francisco, California, USA, 28-30 September 2009; 01/2009