V. Jain

University of California, Irvine, Irvine, CA, United States

Are you V. Jain?

Claim your profile

Publications (15)13.65 Total impact

  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: A W-band direct-detection-based receiver front-end for millimeter-wave passive imaging in a 0.18-m BiCMOS process is presented. The proposed system is comprised of a direct-detection front-end architecture employing a balanced LNA with an embedded Dicke switch, power detector, and base-band circuitry. The use of a balanced LNA with an embedded Dicke switch minimizes front-end noise figure, resulting in a great imaging resolution. The receiver chip achieves a measured responsivity of 20–43 MV/W with a front-end 3-dB bandwidth of 26 GHz, while consuming 200 mW. The calculated NETD of the SiGe receiver chip is 0.4 K with a 30 ms integration time. This work demonstrates the possibility of silicon-based system-on-chip solutions as lower cost alternatives to compound semiconductor multi-chip imaging modules.
    Journal of Solid-State Circuits; 10/2011
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a carrierless RF-correlation-based impulse radio ultra-wideband transceiver (TRX) front-end in a 130-nm CMOS process. Timing synchronization and coherent demodulation are implemented directly in the RF domain, targeting applications such as short-range energy-efficient wireless communication at gigabit/second data rates. The 6-10-GHz band is exploited to achieve higher data rate. Binary phase-shift keying modulated impulse is generated by edge combining the delayed clock signal at a lower frequency of 2 GHz to avoid a more power-hungry phase-locked loop at higher frequency (e.g., 8 GHz). An on-chip pulse shaper inside the pulse generator is designed to provide filtering for an edge-combined signal to comply with the Federal Communications Commission spectrum emission mask. In order to achieve 25-ps delay accuracy and 500-ps delay range for the proposed two-step RF synchronization, a template-based digital delay generation scheme is proposed, which delays the locally generated trigger pulse instead of the wideband pulse itself. Occupying 6.4 mm<sup>2</sup> of chip area, the TRX achieves a maximum data rate of 2 Gb/s and a receiver (RX) sensitivity of -64 dBm with a bit error rate of 10<sup>-5</sup>, while requiring only 51.5 pJ/pulse in the transmitter mode and 72.9 pJ/pulse in the RX mode.
    IEEE Transactions on Microwave Theory and Techniques 05/2011; · 2.23 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Slow-wave coplanar waveguides (SW-CPW) are promising candidates for realization of low-loss and compact on-chip passive components at millimeter-wave (MMW) frequencies. To meet the stringent pattern density requirement of nanoscale CMOS, two types of dummy prefills are proposed. The transmission lines achieve a measured effective dielectric permittivity of 20 and 10, an attenuation of 1 and 0.5 dB/mm, a quality factor of 15 and 20 and a figure-of-merit of 0.2 dB/rad, all at 40 GHz. A W-band front-end receiver based entirely on the characterized SW-CPW with frequency tripler as the LO is measured. The receiver achieves a total gain of 35-dB, a NF of 9-dB, a P-1dB of -40-dBm, a low power consumption of 108mW under 1.2/0.8V and a FOM of 0.49.
    Compound Semiconductor Integrated Circuit Symposium (CSICS), 2010 IEEE; 11/2010
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: A fully-integrated silicon-based 94-GHz direct-detection imaging receiver with on-chip Dicke switch and baseband circuitry is demonstrated. Fabricated in a 0.18-μm SiGe BiCMOS technology (f<sub>T</sub>/f<sub>MAX</sub> = 200 GHz), the receiver chip achieves a peak imager responsivity of 43 MV/W with a 3-dB bandwidth of 26 GHz. A balanced LNA topology with an embedded Dicke switch provides 30-dB gain and enables a temperature resolution of 0.3-0.4 K. The imager chip consumes 200 mW from a 1.8-V supply.
    Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE; 06/2010
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: A fully-integrated silicon-based 94-GHz direct-detection imaging receiver with on-chip Dicke switch and baseband circuitry is demonstrated. Fabricated in a 0.18-µm SiGe BiCMOS technology (f T /f MAX = 200 GHz), the receiver chip achieves a peak imager responsivity of 43 MV/W with a 3-dB bandwidth of 26 GHz. A balanced LNA topology with an embedded Dicke switch provides 30-dB gain and enables a temperature resolution of 0.3-0.4 K. Initial imaging measurements using the chip along with off-chip antennas are also presented. The imager chip consumes 200 mW from a single 1.8-V power supply.
    SPIE Defense, Security, and Sensing; 04/2010
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents the analysis, design and implementation of a millimeter-wave W-band power detector. Fabricated in a 0.18-μm SiGe BiCMOS technology, the detector circuit exhibits a responsivity of 91 kV/W, a noise equivalent power of 0.5 pW/Hz<sup>1/2</sup>, and a noise figure of 29 dB. The power dissipation of the detector is 75 μW. Reasonable agreement between simulations and measurements is obtained. To the authors' best knowledge, the detector in this work achieves the highest responsivity reported to date for any solid-state W-band detector.
    Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2010 Topical Meeting on; 02/2010
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Integration of multi-mode multi-band transceivers on a single chip will enable low-cost millimeter-wave systems for next-generation automotive radar sensors. The first dual-band millimeter-wave transceiver operating in the 22-29-GHz and 77-81-GHz short-range automotive radar bands is designed and implemented in 0.18-¿ m SiGe BiCMOS technology with f<sub>T</sub>/f<sub>max</sub> of 200/180 GHz. The transceiver chip includes a dual-band low noise amplifier, a shared downconversion chain, dual-band pulse formers, power amplifiers, a dual-band frequency synthesizer and a high-speed highly-programmable baseband pulse generator. The transceiver achieves 35/31-dB receive gain, 4.5/8-dB double side-band noise figure, >60/30-dB cross-band isolation, -114/-100.4-dBc/Hz phase noise at 1-MHz offset, and 14.5/10.5-dBm transmit power in the 24/79-GHz bands. Radar functionality is also demonstrated using a loopback measurement. The 3.9 × 1.9-mm<sup>2</sup> 24/79-GHz transceiver chip consumes 0.51/0.615 W.
    IEEE Journal of Solid-State Circuits 01/2010; · 3.06 Impact Factor
  • Source
    V. Jain, B. Javid, P. Heydari
    [Show abstract] [Hide abstract]
    ABSTRACT: Design and implementation of a millimeter-wave dual-band frequency synthesizer, operating in the 24 GHz and 77 GHz bands, are presented. All circuits except the voltage controlled oscillators are shared between the two bands. A multi-functional injection-locked circuit is used after the oscillators to simplify the reconfiguration of the division ratio inside the phase-locked loop. The 1 mm times 0.8 mm synthesizer chip is fabricated in a 0.18 mum silicon-germanium BiCMOS technology, featuring 0.15 mum emitter-width heterojunction bipolar transistors. Measurements of the prototype demonstrate a locking range of 23.8-26.95 GHz/75.67-78.5 GHz in the 24/77 GHz modes, with a low power consumption of 50/75 mW from a 2.5 V supply. The closed-loop phase noise at 1 MHz offset from the carrier is less than -100 dBc/Hz in both bands. The frequency synthesizer is suitable for integration in direct-conversion transceivers for K/W-band automotive radars and heterodyne receivers for 94 GHz imaging applications.
    IEEE Journal of Solid-State Circuits 09/2009; · 3.06 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: The design of a CMOS 22-29-GHz pulse-radar receiver (RX) front-end for ultra-wideband automotive radar sensors is presented. The chip includes a low-noise amplifier, in-phase/quadrature mixers, a quadrature voltage-controlled oscillator (QVCO), pulse formers, and baseband variable-gain amplifiers. Fabricated in a 0.18-mum CMOS process, the RX front-end chip occupies a die area of 3 mm<sup>2</sup>. On-wafer measurements show a conversion gain of 35-38.1 dB, a noise figure of 5.5-7.4 dB, and an input return loss less than -14.5 dB in the 22-29-GHz automotive radar band. The phase noise of the constituent QVCO is -107 dBc/Hz at 1-MHz offset from a center frequency of 26.5 GHz. The total dc power dissipation of the RX including output buffers is 131 mW.
    IEEE Transactions on Microwave Theory and Techniques 09/2009; · 2.23 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: The design of a carrier-less RF-correlation-based IR-UWB TRX front-end in 130 nm CMOS is presented. Timing synchronization and coherent demodulation are implemented directly in the RF domain, enabling energy-efficient wireless communication at Gb/s data rates. A 25 ps timing resolution is achieved by a two-step synchronizer. Occupying 6.4 mm<sup>2</sup> chip area, the TRX achieves a maximum data rate of 2 Gbps and an RX sensitivity of -64 dBm with a BER of 10<sup>-5</sup>, while requiring only 51.5 pJ/pulse in the TX mode and 72.9 pJ/pulse in the RX mode.
    Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE; 07/2009
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents an intuitive analysis and design/fabrication of a millimeter-wave (MMW) divide-by-3 injection-locked frequency divider (ILFD). Implemented in a 0.18 mum BiCMOS technology, the ILFD circuit exhibits an injection locking range of 1.8-2.7 GHz, a measurement-limited operating range of 75.6-78.6 GHz inside a PLL while simulated is from 70.1-82.3 GHz, and a phase noise of -105 dBc/Hz @ 1 MHz offset from the carrier. To the authors' best knowledge, this divide-by-3 ILFD chip achieves the highest operating frequency reported to date inside a silicon-validated frequency synthesizer loop.
    Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09. IEEE Topical Meeting on; 02/2009
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a dual-band millimeter- wave (mmWave) transceiver (TRX) in a 0.18 mum BiCMOS technology (fT/fmax=200/180GHz). The dual-band TRX operates in the 22-to-29GHz and 77- to-81GHz short-range automotive radar bands.
    IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009; 01/2009
  • Source
    V. Jain, B. Javid, P. Heydari
    [Show abstract] [Hide abstract]
    ABSTRACT: The design of a millimeter-wave dual-band phase-locked frequency synthesizer in a 0.18 mum SiGe BiCMOS technology is presented. All circuits except the voltage controlled oscillators (VCOs) are shared between the two bands. A W-band divide-by-3 frequency divider is used inside the loop after the VCOs to simplify division-ratio reconfiguration. The 0.9 mm<sup>2</sup> synthesizer chip exhibits a locking range of 23.8-26.95/75.67-78. 5 GHz with a low power consumption of 50-75 mW from a 2.5 V supply. The closed-loop phase noise at 1 MHz offset from the carrier is less than -100 dBc/Hz in both bands. The proposed frequency synthesizer is suitable for integration in direct-conversion transceivers for K/W-band automotive radars and heterodyne receivers for 94 GHz imaging applications.
    Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE; 10/2008
  • [Show abstract] [Hide abstract]
    ABSTRACT: The design of a CMOS 22-29 GHz pulse-radar receiver (RX) front-end for ultra-wideband (UWB) automotive radar sensors is presented. Fabricated in a 0.18 mum CMOS process, the 3 mm<sup>2</sup> RX chip achieves a conversion gain of 35-38.1 dB, noise figure of 5.5-7.4 dB and input return loss less than -14.5 dB in the 22-29 GHz band. The phase noise of the constituent QVCO is -107 dBc/Hz at 1 MHz offset from a center frequency of 26.5 GHz. The total dc power dissipation of the RX including LO/output buffers is 131 mW.
    Custom Integrated Circuits Conference, 2007. CICC '07. IEEE; 10/2007
  • [Show abstract] [Hide abstract]
    ABSTRACT: In the presence of high-power environmental noise, such as that present in the common substrate and on the power and ground (P/G) rails of a system-on-a-chip (SOC), the current-to-phase relationship for an LC oscillator cannot be assumed linear. This paper presents a simple nonlinear modification to the well-established linear time-variant (LTV) model for phase noise that facilitates a more accurate prediction of oscillator phase noise and jitter in the presence of high-power noise. For low-power noise, this nonlinear model simplifies to the LTV metric. The accuracy of the proposed analytical model is verified through the simulation of a 10 GHz Colpitts oscillator in a 0.18mum CMOS process.
    Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on; 06/2007