[show abstract][hide abstract] ABSTRACT: This paper presents litho friendly circuit techniques for variability resilient low power 8T SRAM. The new local assist circuitry achieves a state-of-the-art low energy and variability resilient WRITE operation and improves the degraded access speed of SRAM cells at low voltages. Differential VSS bias increases the variability resilience. The physical regularity in the layout of local assist circuitry enables litho optimization thereby reducing the area overhead associated with existing local assist techniques. Statistical simulations in 40nm LP CMOS technology reveals 10x reduction in WRITE energy consumption, 103x reduction in write failures, 6.5x improvement in read access time and 31% reduction in the area overhead.
[show abstract][hide abstract] ABSTRACT: Process variability severely impacts the performance of circuits operating in the subthreshold domain. Among other reasons, this mainly stems from the fact that subthreshold current follows a widely spread Log-Normal distribution. In this paper we introduce a new transistor sizing methodology for standard cells. Our premise relies on balancing the N and P network currents based on statistical formulations. Our approach renders more robust cells. We observe up to 57% better performance and 69% lower energy consumption on a set of ISCAS circuits when they are synthesized with our library as opposed to a commercial library in a CMOS 90nm technology.
[show abstract][hide abstract] ABSTRACT: An ultra low energy, 128 kbit 6T SRAM in 90 nm LP CMOS with energy consumption of 4.4 pJ/access, operating at 80 MHz for the wireless sensor applications is developed. The variability resilient and low power techniques developed include innovation in the local architecture with the use of local read/write assist circuitry. The energy-efficient hierarchical bit-lines structure includes low swing global bit-lines and VDD/2 pre-charged short local bit-lines. The innovative Multi-Sized SA redundancy (MS-SA-R) calibration technique for the global read sense amplifiers of the SRAM not only adds to the variability resilience but also yields maximum energy reduction compared with existing calibration techniques.
IEEE Journal of Solid-State Circuits 11/2011; · 3.06 Impact Factor
[show abstract][hide abstract] ABSTRACT: In this paper, the authors present an event-driven system with resources to run applications with different degrees of complexity in an energy-aware way. The architecture uses effective system partitioning to enable duty cycling, SIMD instructions, power gating, voltage scaling, multiclock domains, multivoltage domains, and extensive clock gating. The system has sufficient computational power to run a complex ECG algorithm with feature extraction and motion artifact cancellation or multichannel EEG processing. The system consumes an average of 13 pJ/cycle running a CWT-based ECG application at 0.4 V. The processor can run at voltage range of 0.4 to 1.2 V and supports frequency range of 1 to 100 MHz. The system has comparable energy/cycle, more computation capability, and larger available frequencies than the previously reported complex designs in the works of Sindhara et al.  and Chen et al. .
[show abstract][hide abstract] ABSTRACT: In order for wireless body area networks to meet widespread adoption, a number of security implications must be explored to promote and maintain fundamental medical ethical principles and social expectations. As a result, integration of security functionality to sensor nodes is required. Integrating security functionality to a wireless sensor node increases the size of the stored software program in program memory, the required time that the sensor's microprocessor needs to process the data and the wireless network traffic which is exchanged among sensors. This security overhead has dominant impact on the energy dissipation which is strongly related to the lifetime of the sensor, a critical aspect in wireless sensor network (WSN) technology. Strict definition of the security functionality, complete hardware model (microprocessor and radio), WBAN topology and the structure of the medium access control (MAC) frame are required for an accurate estimation of the energy that security introduces into the WBAN. In this work, we define a lightweight security scheme for WBAN, we estimate the additional energy consumption that the security scheme introduces to WBAN based on commercial available off-the-shelf hardware components (microprocessor and radio), the network topology and the MAC frame. Furthermore, we propose a new microcontroller design in order to reduce the energy consumption of the system. Experimental results and comparisons with other works are given.
Journal of Medical Systems 03/2011; 35(5):1289-98. · 1.78 Impact Factor
[show abstract][hide abstract] ABSTRACT: This paper presents a novel low-to-high level shifter that enables having voltage domains with substantially different supply voltages from near-threshold to full supply voltage. The level shifter was designed in a 90 nm CMOS technology and uses thick-oxide transistors, non-minimum channel length transistors, along with novel circuit structures to up convert from 0.36 V to 1.32 V and all the voltage levels in between for all process corners and the temperature range of [0°C - 125°C]. Relaxing the temperature operating range to [25°C - 125°C], the level shifter works deep into the sub threshold region capable of up converting from 0.31 V to 1.32 V. For the typical case operating condition, the proposed level shifter has an unprecedented performance of 1.5 ns while up converting 0.36 V to 1.32 V.
Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on; 01/2011
[show abstract][hide abstract] ABSTRACT: This design sets a record low energy consumption (average RD/WR) of 2.65pJ/access for a 64kbit embedded SRAM operating at 90MHz in 65nm LP CMOS. This low energy and variability resilient SRAM macro ensures write-ability with an innovative Mimicked Negative Bit-line technique. The novel low energy Charge Limited Sequential sense amplifier consumes 11.36fJ/decision and obtains σVoffset of 14.297mV without requiring calibration. I Introduction Ultra low energy and variability resilient SRAM's for L1 data and instruction memories are vital to meet the power budget requirements of low performance energy scavenging wireless sensor nodes (Figure.1). The increased inter and intra die variations with the technology scaling degrade the IREAD, SNMREAD, write margin (WM) and SA performance of embedded SRAM's. Therefore, it is crucial to improve the operating margins of SRAM without increasing the energy consumption. The decoupled read port 8T SRAM cell enhances the IREAD and SNMREAD, but it does not improve the WM. The SA calibration techniques (1)(2)(4) reduces the SA mismatch offset and achieves the low energy consumption. But it requires a separate calibration phase which limits its applicability (increased test cost). This paper presents a variability resilient and low power SRAM macro based on the divided word line architecture, low swing read bit-lines and hierarchical divided write bit-lines with local write receivers (Figure.2) .The design innovation includes: (1) a proposed write method, Mimicked Negative Bit-Line (MNBL) technique improves the WM and resolves the issues related with the existing Conventional Negative Bit-Line (CNBL) technique (3), and (2) a novel calibration free Charge Limited Sequential sense amplifier (CLS- SA) improves the energy-offset tradeoff and avoids the additional increase in the memory test costs and test time, associated with SAs that rely on calibration to address the process variability.
Proceedings of the 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, Sept. 12-16, 2011; 01/2011
[show abstract][hide abstract] ABSTRACT: Sub-threshold operation has been proven to be very effective to reduce the power consumption of circuits when high performance is not required. Future low power systems on chip are likely to consist of many sub-systems operating at different frequencies and VDDs from super-threshold to sub-threshold region. Synchronizers are therefore needed to interface between these sub-systems. However, VDD scaling rapidly degrades synchronizers' performance making them unsuitable for sub-threshold operation. For the first time, we analyze the synchronizer performance at ultra low voltages and propose to apply forward body bias to extend the operation of synchronizers to the sub-threshold region and to make them resilient to process variation. We show that applying full-VDD bias significantly increases the transconductance of the bi-stable in synchronizers without adding capacitance to the switching nodes. As a result all the circuit parameters (τ metastability time constant, Td normal propagation delay and Tw metastability window) determining synchronizer performance or mean time between failure (MTBF) can be improved by more than 80% (i.e. by five times) in the sub-threshold region. We also study the impact of process variation on the synchronizer performance in the sub-threshold region and conclude that with full-VDD bias the synchronizer MTBF can be improved from seconds to years for the worst case corner. Finally, we propose an implementation scheme of full-VDD body-biased synchronizer, which is able to work for a wide range of VDDs from sub-threshold region to nominal VDD with nearly zero overhead.
[show abstract][hide abstract] ABSTRACT: The cost of health care in first-world countries is increasing dramatically as a result of advances in medicine, a population that is becoming older and an increasingly unhealthy lifestyle. Personal health care concepts where sensors within and around the body monitor and measure all kind of physiological signals can be an addition to medicare with high benefits. This concept allows patients to stay in their home environment and hence have a better quality of life with lower costs involved. For these reasons research and development is ongoing on many body worn and implantable sensor nodes. In this paper it is shown that application knowledge and understanding the contribution of different components to the system power consumption is the best starting point to make optimal trade-offs in the system design. This will minimize the overall power consumption of a sensor node without losing track of the major functionality needed. Besides the importance of system optimization, it is also shown that new components and circuit techniques need to be developed to achieve orders of magnitude increase in energy efficiency. This is a must to realize ultra-thin electrocardiogram patches as well as more demanding nodes with a small form factor like real-time Electro Encephalogram processing for brain computer interaction or neuro-implants.
14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland; 01/2011
[show abstract][hide abstract] ABSTRACT: This paper presents a voltage-scalable digital signal processing system designed for the use in a wireless sensor node (WSN) for ambulatory monitoring of biomedical signals. To fulfill the requirements of ambulatory monitoring, power consumption, which directly translates to the WSN battery lifetime and size, must be kept as low as possible. The proposed processing platform is an event-driven system with resources to run applications with different degrees of complexity in an energy-aware way. The architecture uses effective system partitioning to enable duty cycling, single instruction multiple data (SIMD) instructions, power gating, voltage scaling, multiple clock domains, multiple voltage domains, and extensive clock gating. It provides an alternative processing platform where the power and performance can be scaled to adapt to the application need. A case study on a continuous wavelet transform (CWT)-based heart-beat detection shows that the platform not only preserves the sensitivity and positive predictivity of the algorithm but also achieves the lowest energy/sample for ElectroCardioGram (ECG) heart-beat detection publicly reported today.
IEEE Transactions on Biomedical Circuits and Systems 01/2011; 5:546-554. · 2.74 Impact Factor
[show abstract][hide abstract] ABSTRACT: An Ultra Low Power (ULP) biomedical System-on Chip (SoC) has been developed for efficient ECG/EEG signal processing in a Body Area Network environment. This experimental SoC explores the use of event-driven peripheral modules that autonomously interact with external sensors together with the use of an Application-Specific-Instruction-set Processor (ASIP) to optimize energy-efficiency during active and sleep periods. The SoC has been manufactured in standard 90nm CMOS process and use has been made of power gating to reduce leakage power that starts to become more dominant in advanced technologies. When running an ECG algorithm that is capable of reliably detecting the QRS complex in an ambulatory environment, an average power consumption of 10 μW has been measured at 0.7 V supply.
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian; 12/2010
[show abstract][hide abstract] ABSTRACT: A Variability resilient 128kbit 6T SRAM with energy consumption of 4.4pJ/access, operating at 80MHz for wireless sensor applications is developed in 90nm LP CMOS. The techniques developed include novelty in the local architecture with local read/write assist circuitry. VDD/2 pre-charged short local bit-lines with local sense amplifier enables charge re-cycling and gated read buffers eliminates bit-line leakage The multi-sized sense amplifier redundancy used for global sense amplifiers ensures variability resilient low energy consumption read operation.
[show abstract][hide abstract] ABSTRACT: Ultra low voltage operation promises to reduce power dissipation for wireless sensor network applications. Such ultra low voltage systems are likely to have many sub-systems operating at different frequencies and VDDs from super-threshold to sub-threshold. Synchronizers are needed to interface among these domains. However, VDD scaling rapidly degrades synchronizers performance making them unsuitable for ultra low voltage operation. Here, we analyze the performance of two existing synchronizers at ultra low voltages and propose to apply forward body bias to the synchronizer latch to extend its operation to sub-threshold region with an acceptable performance and to make them process variation resilient. We show that by using full-VDD bias, synchronizer performance can be improved by more than 80%. We also study the impact of process variation on the synchronization time and found that with full-VDD bias 9X improvement in the synchronization time can be achieved for the worst case corner. Finally, we propose a simple implementation scheme of body-biased synchronizer which improves the synchronizer performance significantly at ultra low voltages with nearly zero overhead and can be configured to work for a wide range of VDDs from sub-threshold region to nominal VDD.
16th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2010, Grenoble, France, 3-6 May 2010; 01/2010
[show abstract][hide abstract] ABSTRACT: Power gating (PG) has emerged as an effective technique to reduce standby leakage power in portable devices where battery life time is vital. However, it comes at the cost of timing overhead which is a problem for most of the applications where real-time constraints exist. Designing efficient power gated circuits is very challenging problem due to contrasting requirements in active mode (low timing overhead implying larger power switch size) and standby mode (low standby leakage power implying smaller power switch size). In this work, we show that applying Forward Body Biasing (FBB) to the logic gates in conjunction with power gating (PG + FBB) will provide us with an additional degree of freedom which can be utilized to improve the efficiency of the power gated circuit. We propose an optimization algorithm to find the optimum power switch size and FBB value such that total leakage energy of the design (active + standby) in minimized. Results show that our PG + FBB technique on an average improves the leakage energy savings by 2X-5X as compared to using only power gating. With PG + FBB technique, one can also design a zero delay penalty power gated circuit which is not possible if only power gating is used.