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Xingui Zhang,
Huaxin Guo,
Hau-Yu Lin,
Chao-Ching Cheng,
Chih-Hsin Ko,
Clement H. Wann, Guang-Li Luo,
Chun-Yen Chang,
Chao-Hsin Chien,
Zong-You Han,
Shih-Chiang Huang,
Hock-Chun Chin,
Xiao Gong,
Shao-Ming Koh,
Phyllis Shi Ya Lim,
Yee-Chia Yeo
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ABSTRACT: The demonstration of a salicidelike self-aligned contact technology for III-V metal-oxide-semiconductor field-effect transistors (MOSFETs) is reported. A thin and continuous crystalline germanium-silicon (GeSi) layer was selectively formed on n <sup>+</sup> doped gallium arsenide (GaAs) regions by epitaxy. A new self-aligned nickel germanosilicide (NiGeSi) Ohmic contact with good morphology was achieved using a two-step annealing process with precise conversion of the GeSi layer into NiGeSi. NiGeSi contact with the contact resistivity (ρ<sub>c</sub>) of 1.57 Ω mm and sheet resistance (R<sub> sh </sub>) of 2.8 Ω/◻ was achieved. The NiGeSi-based self-aligned contact technology is promising for future integration in high performance III-V MOSFETs.
Journal of vacuum science & technology. B, Microelectronics and nanometer structures: processing, measurement, and phenomena: an official journal of the American Vacuum Society 06/2011; · 1.34 Impact Factor
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Guang-Li Luo,
Zong-You Han,
Chao-Hsin Chien,
Chih-Hsin Ko,
Clement H. Wann,
Hau-Yu Lin,
Yi-Ling Shen,
Cheng-Ting Chung,
Shih-Chiang Huang,
Chao-Ching Cheng,
Chun-Yen Chang
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ABSTRACT: Ge films were epitaxially grown on GaAs(100) substrates and
(100) virtual substrates using an ultrahigh vacuum/chemical vapor deposition system. The incubation time of Ge growth depends
on Ga(In)As surfaces that were processed by different wet chemical solutions. Growth behaviors, such as island growth at the
initial stages and selective growth into recessed regions of GaAs, were studied by transmission electron microscopy. To test
the quality of Ge grown on GaAs, an
diode was fabricated. We propose that through Ge selective epitaxial growth, Ge can be used as the source–drain of a GaAs
metal-oxide-semiconductor field-effect transistor (MOSFET) to overcome some intrinsic limitations of this device.
Journal of The Electrochemical Society. 12/2009; 157(1):H27-H30.
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ABSTRACT: In this paper, we investigated the characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited- Al<sub>2</sub>O<sub>3</sub> gate dielectrics. The magnitudes of the rectifying ratios for the Ge p<sup>+</sup>-n and n<sup>+</sup>-p junctions exceeded three and four orders of magnitude (in the voltage range of plusmn1 V), respectively, with accompanying reverse leakages of ca. 10<sup>-2</sup> and 10<sup>-4</sup> A ldr cm<sup>-2</sup>, respectively. The site of the primary leakage path, at either the surface periphery or junction area, was determined by the following conditions: 1) the thermal budget during dopant activation, and 2) whether forming gas annealing (FGA) was employed or not. In addition, performing FGA at 300degC boosted the device on-current, decreased the Al<sub>2</sub>O<sub>3</sub>/Ge interface states to 8 times 10<sup>11</sup> cm<sup>-2</sup> ldr eV<sup>-1</sup>, and improved the reliability of bias temperature instability. The peak mobility and on/off ratio reached as high as 225 cm<sup>2</sup> ldr V<sup>-1</sup> ldr s<sup>-1</sup> and > 10<sup>3</sup>, respectively, for the p-FET ( W / L = 100 mum/4 mum), while these values were less than 100 cm<sup>2</sup> ldr V<sup>-1</sup> ldr s<sup>-1</sup> and ca. 10<sup>3</sup>, respectively, for the n-FET ( W / L = 100 mum/9 mum). The relatively inferior n-FET performance resulted from the larger source/drain contact resistance, higher surface states scattering, and lower substrate-doping concentration.
IEEE Transactions on Electron Devices 09/2009; · 2.32 Impact Factor
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ABSTRACT: We investigated the selective growth of germanium into nanoscale trenches on silicon substrates. These nanoscale trenches,
the smallest size of which was 50 nm, were fabricated using the state-of-the-art shallow trench isolation technique. The quality
of the Ge films was evaluated using transmission electron microscopy. The formation of threading dislocations (TDs) was effectively
suppressed when using this deposition technique. For the Ge grown in nanoscale Si areas (e.g., several tens of nanometers),
the TDs were probably readily removed during cyclic thermal annealing predominantly because their gliding distance to the
sidewalls was very short. Therefore, nanoscale epitaxial growth technology can be used to deposit Ge films on lattice-mismatched
Si substrates with a reduced defect density.
Journal of The Electrochemical Society. 08/2009; 156(9):H703-H706.
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ABSTRACT: In this paper, we present MEDICI simulations of the admittance-voltage properties of Ge and Si MOS devices, including analyses of substrate conductance G <sub>sub</sub> and high-low transition frequency f <sub>tran</sub>, to explore the differences in the minority-carrier response. The Arrhenius-dependent G <sub>sub</sub> characteristics revealed that a larger energy loss-by at least four orders of magnitude-occurs in Ge than in Si, reflecting the fast minority-carrier response rate, i.e., a higher value of f <sub>tran</sub>. We confirmed that the higher intrinsic carrier concentration in Ge, through the generation/recombination of midgap trap levels as well as the diffusion mechanism, resulted in the onset of low-frequency C - V curves in the kilohertz regime, accompanying the gate-independent inversion conductance. The experimental data obtained from Al<sub>2</sub>O<sub>3</sub>/Ge MOS capacitors were consistent with the values of G <sub>sub</sub> and f <sub>tran</sub> obtained from MEDICI predictions and theoretical calculations. In addition, upon increasing the inversion biases, we observed shifts in the G <sub>sub</sub>/ f conductance peaks to low frequencies that mainly arose from the transition of minority carriers with bulk traps in the depletion layer. Meanwhile, we estimated that the bulky defects of ca. ( 2-4) ×10<sup>15</sup> cm<sup>-3</sup> exist in present-day low-doped Ge wafers.
IEEE Transactions on Electron Devices 06/2009; · 2.32 Impact Factor
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ABSTRACT: High source/drain concentration level, ultrashallow junction, and high-mobility channel are important for the requirements of nanoscale transistors. Microwave processing of semiconductors could offer distinct advantages over conventional RTP systems in some applications, and the anneal temperature is within the range of 300<sup>deg</sup>C-500<sup>deg</sup>C. By using a low-temperature microwave anneal, the sheet resistance and boron diffusion in the Si/Ge/Si substrate could be reduced effectively, and the crystalline structure of Si/Ge/Si is not damaged according to the TEM image and the XRD signals.
IEEE Electron Device Letters 03/2009; · 2.85 Impact Factor
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ABSTRACT: We have evaluated the thermal conductivity of Si/SiGe superlattice films by theoretical analysis and experiment. In experiments, the ultrahigh vacuum chemical vapor deposition is employed to form the Si / Si <sub>0.71</sub> Ge <sub>0.29</sub> and Si / Si <sub>0.8</sub> Ge <sub>0.2</sub> superlattice films. The cross-plane thermal conductivities of these superlattice films are measured based on the 3ω method. In the theoretical analysis, the phonon transport in Si / Si <sub>1-x</sub> Ge <sub>x</sub> superlattice film is explored by solving the phonon Boltzmann transport equation. The dependence of the thermal conductivity of the Si / Si <sub>1-x</sub> Ge <sub>x</sub> superlattice films on the superlattice period, the ratio of layer thicknesses, and the interface roughness is of interest. The calculations show that when the layer thickness is on the order of one percentage of the mean free path or even thinner, the phonons encounter few intrinsic scatterings and consequently concentrate in the directions having high transmissivities. Nonlinear temperature distributions are observed near the interfaces, arising from the size confinement effect and resulting in a slight increase in the film thermal resistances. The interface resistance due to the interface scattering/roughness, which is nearly independent of the film thickness, nonetheless dominates the effective thermal conductivity, especially when the superlattice period is small. Finally the experimental measurements agree with the theoretical predictions if the specular fraction associated with the interface is properly taken.
Journal of Applied Physics 01/2009; · 2.17 Impact Factor
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ABSTRACT: In this study we investigated the interfacial chemistry occurring between an atomic-layer-deposited Al <sub>2</sub> O <sub>3</sub> high- k film and a GaAs substrate and the impact of sulfidization and thermal annealing on the properties of the resultant capacitor. We observed that sulfide passivation of the Al <sub>2</sub> O <sub>3</sub>/ Ga As structure improved the effect of Fermi level pinning on the electrical characteristics, thereby providing a higher oxide capacitance, smaller frequency dispersion, and reduced surface states, as well as decreased interfacial charge trapping and gate leakage currents. Photoemission analysis indicated that the ( N H <sub>4</sub>)<sub>2</sub> S -treated GaAs improved the quality of the as-deposited Al <sub>2</sub> O <sub>3</sub> thin film and preserved the stoichiometry of the dielectric during subsequent high-temperature annealing. This behavior was closely correlated to the diminution of GaAs native oxides and elemental arsenic defects and their unwanted diffusion. In addition, thermal processing under an O <sub>2</sub> atmosphere, relative to that under N <sub>2</sub> , decreased the thickness of the Al <sub>2</sub> O <sub>3</sub> gate dielectric and relieved the gate leakage degradation induced by metallic arsenic; as a result, superior dielectric reliability was attained. We discuss the underlying thermochemical reactions that account for these experimental observations.
Journal of Applied Physics 05/2008; · 2.17 Impact Factor
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ABSTRACT: In this study we demonstrated improved electrical characteristics of
dielectric thin films on n-GaAs substrate by manipulating wet-chemical clean and
passivation. With X-ray photoelectron spectroscopy analysis, the HCl-cleaned GaAs surface was characterized to possess oxide
species mainly in the form of
near the outmost surface and
with elemental arsenic close to the interface. These undesirable components could be suppressed through rinsing in
alkaline solution and then performing sulfidization at
, resulting in alleviating the Fermi level pinning effect on
capacitor performance. Higher oxide capacitance and alleviated frequency dispersion at the accumulation/depletion regimes
were achieved, accompanied by negligible charge trapping
. Accordingly, gate leakage
was lowered to ca.
at gate voltage
, which was comparable to the recently reported performance of
structure with an ultrathin
interfacial layer. We attributed the electrical improvements to the enhanced stabilization of high-
/sulfur-terminated GaAs interface due to abatement of native oxides and excess arsenic segregation.
Journal of The Electrochemical Society. 02/2008; 155(3):G56-G60.
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ABSTRACT: We studied the thermal stability of the as-deposited
thin films on the Ge substrate by employing rapid thermal annealing. After undergoing high-temperature processing, we observed
several interesting physical and electrical features presented in the
system, including a large Ge out-diffusion (
atom %) into high-
films, positive shift of the flatband voltage, severe charge trapping, and increased leakage current. These phenomena are
closely related to the existence of
defective layer and the degree of resultant GeO volatilization. We abated these undesirable effects, especially for reducing
the amount of Ge incorporation (
atom %) and the substoichiometric oxide at dielectric-substrate interface, through performing
plasma pretreatment on the Ge surface. These improvements can be interpreted in terms of a surface nitridation process that
enhanced the thermal stability of the high-
interface. In addition, we measured that the conductance loss in inversion was still high and it revealed independence with
respect to gate bias, reflecting the fact that the minority carriers in Ge can rapidly respond either through a diffusion
mechanism or through midgap trap states residing in Ge bulk substrates.
Journal of The Electrochemical Society. 06/2007; 154(7):G155-G159.
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ABSTRACT: In this study the authors investigated the Ge outdiffusion characteristics of HfOxNy/Ge metal-insulator-semiconductor capacitors to determine their charge trapping behavior. Capping the Ge substrate with an ultrathin Si layer inhibits the incorporation of Ge into the high-k bulk dielectric in the form of GeOx, thereby diminishing the resultant oxide charge trapping. The thermal stability of the entire capacitor structure was also improved after performing an additional Si passivation process.
Applied Physics Letters 01/2007; 90(1):012905-012905-3. · 3.84 Impact Factor
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ABSTRACT: We have studied the thermochemical characteristics of ZrOx(Ny)/Ge and Si interfaces by employing postdeposition annealing. We found that Ge oxide species severely desorbed from the inherent interfacial layer, which was speculated to retard the formation of Zr germanate during high-temperature processing. These unique features enable ZrOx(Ny)/Ge gate stack to show a better equivalent-oxide-thickness scalability as compared to ZrOx(Ny)/Si gate stack. However, the volatilization of GeOx-contained interfacial layer also caused the formation of small pits and/or holes in the overlying ZrOx(Ny) gate dielectrics, which was expected to cause deterioration in the electrical properties of fabricated high-k/Ge devices.
Applied Physics Letters 07/2006; 89(1):012905-012905-3. · 3.84 Impact Factor
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ABSTRACT: In this study we used a low-pressure metal organic vapor phase epitaxy method to investigate the growth of GaAs metal gate semiconductor field effect transistor MESFET structures on a Si substrate. The buffer layer between the Si substrate and the grown GaAs epitaxial layers was a composite Ge/ Si 0.05 Ge 0.95 /Si 0.1 Ge 0.9 metamorphic layer. We used transmission electron microscopy to observe the microstructures formed in the grown GaAs/ Ge/ Si x Ge 1−x / Si material and atomic force microscopy to analyze the surface morphology and the formation of antiphase domains in the GaAs epitaxial layers. The measured Hall electron mobility in the channel layer of a MESFET structure grown on a 6° misoriented Si substrate was 2015 cm 2 V −1 s −1 with a carrier concentration of 5.0 10 17 cm −3 . The MESFET device fabricated on this sample exhibited good current-voltage characteristics. © 2007 American Institute of Physics.
