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C. Prasad,
P. Bai, S. Gannavaram,
W. Hafez,
J. Hicks,
C. Jan,
J. Lin,
M. Jones,
K. Komeyli,
R. Kotlyar,
K. Mistry,
I. Post,
C. Tsai
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ABSTRACT: In this paper, we present extensive reliability characterization results for a novel dual gate 45 nm HK+MG technology. BTI, HCI and TDDB degradation modes on the Logic and I/O transistors are studied and excellent reliability is demonstrated. Emphasis is placed on the importance of process optimizations to support robust I/O transistors while maintaining the high performance and reliability of Logic transistors. Monitoring of reliability for HVM and collateral reliability are also addressed.
Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
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C.-H. Jan,
M. Agostinelli,
M. Buehler,
Z.-P. Chen,
S.-J. Choi,
G. Curello,
H. Deshpande, S. Gannavaram,
W. Hafez,
U. Jalan, [......],
H. Tashiro,
C. Tsai,
P. Vandervoorn,
J. Xu,
L. Yang,
J.-Y. Yeh,
J. Yip,
K. Zhang,
Y. Zhang,
P. Bai
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ABSTRACT: A leading edge 32 nm high-k/metal gate transistor technology has been optimized for SoC platform applications that span a wide range of power, performance, and feature space. This technology has been developed to be modular, offering mix-and-match transistors, interconnects, RF/analog passive elements, embedded memory, and noise mitigation options. The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently. Embedded memories include high density (0.148 um<sup>2</sup>) and low voltage (0.171 um<sup>2</sup>) SRAMs as well as secure OTP fuses. Analog/RF SoC features include high precision, high quality passives (resistors, capacitors and inductors) and deep-nwell noise isolation.
Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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C.-H. Jan,
P. Bai,
S. Biswas,
M. Buehler,
Z.-P. Chen,
G. Curello, S. Gannavaram,
W. Hafez,
J. He,
J. Hicks, [......],
J. Rizk,
G. Sacks,
H. Tashiro,
D. Towner,
C. Tsai,
Y. Wang,
L. Yang,
J.-Y. Yeh,
J. Yip,
K. Mistry
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ABSTRACT: A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have been achieved at 1.1 V and off-state leakage of 1 nA/um. Record RF performance for a mainstream 45 nm bulk CMOS technology has been achieved with measured f<sub>T</sub>/f<sub>MAX</sub> values of 395 GHz/410 GHz for NMOS and 300 GHz/325 GHz for PMOS with 28 nm L<sub>gate</sub> transistors. HV I/O transistors with robust reliability and other SOC features, including linear resistors, MIS and MIM capacitors, varactors, inductors, vertical BJTs, precision diodes and high density OTP fuses are employed for HV I/O, analog and RF circuit integration.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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I. Post,
M. Akbar,
G. Curello, S. Gannavaram,
W. Hafez,
U. Jalan,
K. Komeyii,
J. Lin,
N. Lindert,
J. Park,
J. Rizk,
G. Sacks,
C. Tsai,
D. Yeh,
P. Bai,
C.-H. Jan
[show abstract]
[hide abstract]
ABSTRACT: Record breaking RF performance was recently achieved on a 65nm CMOS technology (29nm L<sub>gate</sub>, 210nm pitch) employing uni-axial strained silicon transistors. These highest-reported cutoff frequencies for NMOS transistors achieve f<sub>T</sub>/f<sub>MAX</sub> values of 360 GHz/420 GHz. PMOS transistors also demonstrate superior performance with f<sub>T</sub>/f<sub>MAX</sub> values of 238 GHz/295 GHz. Varactor performance on this substrate technology is also discussed
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
