Publications (9)4 Total impact

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    ABSTRACT: Extreme Ultraviolet (EUV) lithography is a leading technology option for manufacturing at the 22nm half pitch node and beyond. Implementation of the technology will require continued progress on several key supporting infrastructure challenges, including EUV photoresist materials. The main development issue regarding EUV photoresists is simultaneously achieving the high resolution, high sensitivity, and low line width roughness (LWR) required. This paper describes our strategy, the current status of EUV materials, and some integrated post-development LWR reduction efforts. Data collected utilizing Intel′s Micro-Exposure Tool (MET) is presented in order to examine the feasibility of establishing a resist process that simultaneously exhibits ≤22nm half-pitch (HP) L/S resolution at ≤11.3mJ/cm2 with ≤3nm LWR
    Journal of Photopolymer Science and Technology 01/2011; 24(2):127-136. DOI:10.2494/photopolymer.24.127 · 0.91 Impact Factor
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    ABSTRACT: The International Technology Roadmap for Semiconductors (ITRS) denotes Extreme Ultraviolet (EUV) lithography as a leading technology option for realizing the 22nm half pitch node and beyond. According to recent assessments made at the 2010 EUVL Symposium, the readiness of EUV materials remains one of the top risk items for EUV adoption. The main development issue regarding EUV resists has been how to simultaneously achieve high resolution, high sensitivity, and low line width roughness (LWR). This paper describes our strategy, the current status of EUV materials, and the integrated post-development LWR reduction efforts made at Intel Corporation. Data collected utilizing Intel's Micro- Exposure Tool (MET) is presented in order to examine the feasibility of establishing a resist process that simultaneously exhibits
    Proceedings of SPIE - The International Society for Optical Engineering 03/2010; DOI:10.1117/12.879641 · 0.20 Impact Factor
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    ABSTRACT: This paper describes integration of an advanced composite high-K gate stack (4nm TaSiO<sub>x</sub>-2nm InP) in the In<sub>0.7</sub>Ga<sub>0.3</sub>As quantum-well field effect transistor (QWFET) on silicon substrate. The composite high-K gate stack enables both (i) thin electrical oxide thickness (t<sub>OXE</sub>) and low gate leakage (J<sub>G</sub>) and (ii) effective carrier confinement and high effective carrier velocity (V<sub>eff</sub>) in the QW channel. The L<sub>G</sub>=75nm In<sub>0.7</sub>Ga<sub>0.3</sub>As QWFET on Si with this composite high-K gate stack achieves high transconductance of 1750¿S/¿m and high drive current of 0.49mA/¿m at V<sub>DS</sub>=0.5V.
    Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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    ABSTRACT: A 15-nm node floating body cell (FBC) memory was demonstrated utilizing silicon on replacement insulator (SRI) technology on bulk substrate. Highly selective SiGe etch and nano-scale anchors enabled the fabrication of silicon on thin replacement oxide of 12 nm. The memory characteristics show a memory signal of 7 μA and disturb retention time of 20 ms for a 51-nm gate length and 77-nm width device. This is the best FBC memory performance reported on bulk substrate.
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    ABSTRACT: In order to meet the linewidth roughness (LWR) requirements for the 16 nm node, postprocessing methods need to be investigated to reduce the LWR after the lithography step. We present the results of five different techniques applied to a single extreme ultraviolet photoresist. The results show that rinse has the most promise in achieving the nearly two time LWR improvement needed. However, other techniques such as etch/trim, hardbake, vapor smoothing, and ozonation give at least 10%–20% LWR reduction and could be further optimized. Some of the physical based techniques which melt the photoresist reduce the midspatial frequency (50–10 nm period) roughness, whereas chemical based techniques reduce the low order spatial frequencies (∼500–50 nm period). Hence, a combination of techniques may be the ultimate solution.
    Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures 11/2008; 26(6). DOI:10.1116/1.3013860 · 1.36 Impact Factor
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    ABSTRACT: An aggressively scaled, self-aligned, independently controlled double-gate floating body cell (IDG FBC) is reported. This structure eases the scaling constraints of other FBC memory devices proposed to date. Enhanced memory performance has been demonstrated owing to the independent back gate with thin oxide and thin Si fin. Memory devices with 85-nm Lg and 30-nm fin widths (Z) have been shown to exhibit better memory characteristics at a lower voltage than alternative FBC structures at comparable dimensions. Design, fabrication, operation, and scalability of IDG FBC devices are discussed
    Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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    ABSTRACT: In this paper we present the latest results on developing and integrating extreme ultraviolet lithography (EUVL) at Intel. The world’s first commercial EUV exposure tool was installed in Intel’s development fab, linked to a resist track, and had successfully demonstrated key tool specifications by the end of 2004. Exercising this micro-exposure tool (MET) is a significant step in the path toward inserting EUVL into high-volume manufacturing. Full patterning development of the small features required for the 32nm node are enabled by coupling the high-resolution printing capability of the MET with a state-of-the-art wafer fabrication facility. Moreover, using the MET in a fab environment assists in the identification and resolution of issues associated with the novel aspects of EUVL. We are actively using this tool to study EUV resists, novel processing, and masks. Results of these studies are presented here. Data include imaging performance for both line-space and contact hole patterns on relevant substrates, early etch results, and a mask defect printability study.
    Microelectronic Engineering 04/2006; 83(4):672-675. DOI:10.1016/j.mee.2005.12.037 · 1.34 Impact Factor
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    ABSTRACT: We have combined the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering. High performance NMOS and PMOS trigate transistors are demonstrated with I<sub>DSAT</sub>=1.4 mA/mum and 1.1 mA/mum respectively (I<sub>OFF</sub>=100nA/mum, V<sub>CC </sub>=1.1V and L<sub>G</sub>=40nm) with excellent short channel effects (SCE)-DIBL and subthreshold swing, DeltaS. The contributions of strain, the lang100rang vs. lang110rang substrate orientations, high-k gate dielectrics, and low channel doping are investigated for a variety of channel dimensions and FIN profiles. We observe no evidence of early parasitic corner transistor turn-on in the current devices which can potentially degrade I<sub>ON</sub>-I<sub>OFF</sub> and DeltaS
    VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on; 01/2006
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    ABSTRACT: Intel"s recent 157nm fluoropolymer photoresist development is described, including the benchmarking of photoresist patterning and the suitability of resists in typical Intel etch processes. The imaging results show that the new ultra-low absorbance resists (absorbance
    Proceedings of SPIE - The International Society for Optical Engineering 01/2003; DOI:10.1117/12.483730 · 0.20 Impact Factor