A. Sanasi

University of Pavia, Ticinum, Lombardy, Italy

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Publications (4)2.06 Total impact

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    ABSTRACT: In this paper, the feasibility of partial-RESET programming in phase-change memories is experimentally investigated by considering both the single-cell behavior and the effects of parameter spreads over a memory array. The aim of this paper is to highlight advantages and drawbacks of partial-RESET programming from the viewpoint of multilevel (ML) storage. Although high reproducibility of a partial-RESET programming curve of a single cell has been observed, the parameter spreads over the array imply the need for a program-and-verify (P&V) approach to achieve the necessary accuracy for ML storage. In order to demonstrate the feasibility of partial-RESET ML programming, 4 log-spaced levels within the available resistance window have been programmed by means of a staircase-up P&V algorithm.
    IEEE Transactions on Electron Devices 11/2010; · 2.06 Impact Factor
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    ABSTRACT: In this work, staircase-up (SCU) partial-RESET programming in Phase Change Memories is experimentally investigated at both the single cell and the array level. The aim of this work is to highlight advantages and drawbacks of partial-RESET programming from the viewpoint of multilevel (ML) storage, where the cell can be programmed to any among n >2 predetermined different states. Although high reproducibility of the SCU partial-RESET programming curve of a single cell has been observed, the spread over the considered array implies the need for a Program-and-Verify (P&V) approach to achieve the necessary accuracy for ML storage. The feasibility of SCU P&V partial-RESET programming is experimentally demonstrated for the case of 4 log-spaced levels within the available resistance window.
    Ph.D. Research in Microelectronics and Electronics (PRIME), 2010 Conference on; 08/2010
  • [show abstract] [hide abstract]
    ABSTRACT: In this work, a physics-based analytical model for the partial-RESET operation in Phase Change Memories is proposed. The model describes the electro-thermal behavior of the memory cell and gives an insight into the dynamical phenomena involved in the amorphization process inside the chalcogenide layer. Simulations are compared to measurements carried out on a 180-nm PCM experimental chip based on the μ-trench cell architecture, showing good accuracy of the proposed model both in the case of single pulse programming and in the case of staircase-up partial-RESET programming.
    01/2010;
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    ABSTRACT: The capability to handle multi-level cells is an appealing challenge to reach a high degree of integration also in the field of phase change memories (PCMs). To this aim, tight current (or bit) distributions are needed so as to allocate all programmed levels in the allowed window. As opposed to the above requirement, technology driven spreads tend to increase when the memory cell shrinks to nanoscale sizes, and even atomic scale fluctuations can play an important role. In this scenario, the present work provides a new physically based approach that allows describing the statistical spread for the bit distributions of PCM arrays through a viable and flexible SPICE-like model.
    Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European; 10/2009