B. Nikolic

Hitachi, Ltd., Tokyo, Tokyo-to, Japan

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Publications (3)3.06 Total impact

  • D. Stepanovic, B. Nikolic
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    ABSTRACT: This paper presents a power- and area-efficient 24-way time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) that achieves 2.8 GS/s and 8.1 ENOB in 65 nm CMOS. To minimize the power and the area, the capacitors in the capacitive DAC are sized to meet the thermal noise requirements rather than the matching requirements, leading to the LSB capacitance of 50 aF. An on-chip digital background calibration is used to calibrate the capacitor mismatches in individual ADC channels, as well as the inter-channel offset, gain and timing mismatches. Measurement results at the 2.8 GS/s sampling rate show that the ADC chip prototype consumes 44.6 mW of power from a 1.2 V supply while achieving peak SNDR of 50.9 dB and retaining SNDR higher than 48.2 dB across the entire first Nyquist zone with a $1.8{rm V} _{{rm pp}mathchar"702D {rm diff}}$ input signal. The prototype chip occupies an area of 1.03$,times,$1.66 ${rm mm}^{2}$, including the pads and the testing circuits. The figure of merit (FoM) of this ADC, calculated with the minimum SNDR in the first Nyquist zone, is 76 fJ/conversion-step.
    IEEE Journal of Solid-State Circuits 01/2013; 48(4):971-982. · 3.06 Impact Factor
  • D. Stepanovic, B. Nikolic
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a power- and area-efficient 24-way time-interleaved SAR ADC designed in 65nm CMOS. At 2.8GS/s sampling rate the ADC consumes 44.6mW of power from a 1.2V supply while achieving peak SNDR of 50.9dB and retaining SNDR higher than 48.2dB across the entire first Nyquist zone.
    VLSI Circuits (VLSIC), 2012 Symposium on; 01/2012
  • [Show abstract] [Hide abstract]
    ABSTRACT: The high-speed and high-resolution ADC is a key enabler for many future wireless communications systems. The digital background calibration technique can be used to reduce the total power consumption by enhancing the linearity without using high-gain amplifiers. One of the main practical constraints in the wireless applications is a short time available for calibration. This paper proposes a novel fast calibration method of pipelined ADCs, suitable for wireless communications applications, where a sufficiently high resolution can be achieved without requiring any calibration period.
    Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on; 09/2008