W.H. Teh,
R. Caramto, J. Qureshi,
S. Arkalgud,
M. O'Brien,
T. Gilday,
K. Maekawa,
T. Saito,
K. Maruyama,
T. Chidambaram,
W. Wang,
D. Marx,
D. Grant,
R. Dudley
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ABSTRACT: We report a process development route towards 300 mm production-worthy non-Bosch through-silicon-via (TSV) etch with critical dimensions and via spacing between 1-5 mum and aspect ratios (ARs) up to 20:1 for 3D logic integration. This was performed on an experimental alpha-tool from Tokyo Electron: a magnetically enhanced capacitively coupled plasma etcher with a dipole ring magnet upgrade that aims to capture the strengths (anisotropicity, profile uniformity) while reducing the weaknesses (scalloping, undercut, residues) of a nominal Bosch process. Trending experiments were performed to understand key modulators that contribute to the control of sidewall taper and roughness, etched TSV volume and depth, mask undercut, local bowing effects, and within wafer (WIW) center-to-edge depth and profile uniformity. Selected process-of-records in fabricating TSVs with nominal sizes of 5 mum times 25 mum, 5 mum times 40 mum and 1 mum times 20 mum with ~ 1% WIW depth uniformity, negligible silicon scalloping/mask undercut, and good profile control were developed. These include vertical TSVs and tapered TSVs for different 3D wafer stacking applications. For TSV metrology, assessments were conducted using wafer thickness sensor technology (Tamar Technology, Inc) that is not limited by AR: an optical, non-invasive, and high throughput sensor that measures the etched depth of vias using backside IR illumination. In having a continuous 2 kAring TEOS oxide liner/100 Aring Ta(TaN) barrier/5 kAring Cu seed stack enabled by TSV etch, Cu-filled TSVs of 3 mum times 20 mum and 5 mum times 25 mum were demonstrated.
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on; 10/2009
