J. Daniels

KU Leuven, Leuven, VLG, Belgium

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Publications (6)6.72 Total impact

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    ABSTRACT: A pulse digitizing approach for time-of-arrival pulse radio based ranging is introduced. It is based on a bank of time-to-digital converter (TDC) cores. A comparator bank triggers these multiple TDCs. This multiple event approach has advantages over classic single TDC solutions when facing unknown channel gains, noise corruption, and strong fading channel behavior. Pulses are digitized in a way that is superior in terms of performance versus power to classic A/D conversion. A power effort figure ξ and a new SNDR metric are introduced, easing performance comparison of pulse digitizers. A low power 8 channel digitizing system with a resolution of δt<sub>ring</sub>=62.5 ps is presented for a cm accurate ranging application. The asynchronous, event-based nature of the architecture requires nonstrobed comparators to fire value crossing events. A dynamic range of 800:1 is realized. The digitization device is designed for 130 nm standard CMOS. An analog-baseband front-end I-Q energy detection and comparator threshold level configuration D/As are added to the design. The complete system is designed to consume 4 mW.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 12/2011; · 2.24 Impact Factor
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    ABSTRACT: An analog-to-digital conversion (ADC) scheme based on asynchronous ΔΣ modulation and time-to-digital conversion is presented. An asynchronous ΔΣ modulator translates the analog input to an asynchronous duty-cycle modulated signal. Next, the edge locations are digitally measured using a time-to-digital converter (TDC). This information is then digitally processed into a conventional digital signal. The performance of this novel ADC scheme is theoretically analyzed and verified with simulations. With the proposed digital demodulation algorithm, 11-bit resolution can be obtained with an overcycling ratio (OCR) of only four, which is suitable for high bandwidth applications such as very high bit-rate digital subscriber line (VDSL). When a higher OCR can be tolerated, a gated ring-oscillator (GRO) TDC with an inherent first-order noise shaping property is suggested in combination with a digital continuous-time moving-average (CTMA) filter. This allows for resolutions in excess of 13 bits, which is suitable for ADSL2+. The proposed technique shifts the complexity toward the digital domain, leading to more compact ADC and reduced power consumption, and is, therefore, particularly suited for ADC in ultralow-voltage nanometer technologies that are used for high-speed data communication applications.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 10/2010; · 2.24 Impact Factor
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    ABSTRACT: A 300MHz all-digital differential VCO-based ADC occupies 0.02mm<sup>2</sup> in 65nm CMOS, achieving a peak SFDR of 79dB and an SNDR of 64dB over a 30MHz BW. This high linearity is obtained using two VCOs in differential configuration in combination with an 11-points digital calibration. The power consumption is 11.4mW and the FOM is 150fJ/conv. step.
    VLSI Circuits (VLSIC), 2010 IEEE Symposium on; 07/2010
  • J. Daniels, W. Dehaene, M. Steyaert
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    ABSTRACT: Voltage-controlled oscillator-based analog-to-digital converters utilizes the superior time resolution and digital processing power of time-domain signal processing. With its inherent first-order noise shaping property, very high accuracy can be obtained while reducing both area and power consumption. An all-digital VCO-based ADC scheme is presented which combines a differential configuration with digital calibration to obtain very high linearity. A coarse-fine quantization approach is used to reduce the circuit complexity compared to the traditional multi-bit quantization The phase resolution is increased using passive interpolation coupled VCOs. These techniques are illustrated with a 65 nm CMOS implementation of a 30 MHz BW 10-bit ADC, occupying only 0.023 mm<sup>2</sup>.
    Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on; 07/2010
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    ABSTRACT: A combined Time-to-Digital Digital-to-Time Converter (TDC-DTC) is presented for use in a high-precision single-bit Asynchronous DeltaSigma ADC. It quantizes the 1-bit asynchronous square wave with 61 ps precision, obtaining a virtual sampling frequency of 16.4 GHz with only a 350 MHz clock. Measurements confirm that with this precision, the design of a single-bit Asynchronous DeltaSigma ADC obtaining 78 dB SNDR over a 500 kHz bandwidth is feasible using only a first-order noise shaping and with a limit cycle frequency of only 8 MHz. With this technique, both the order and the bandwidth requirements of the noise shaping filter can be relaxed, which significantly reduces the analog complexity of the DeltaSigma Modulator. The proposed architecture is therefore especially suited for low-voltage nanometer technologies.
    Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian; 12/2008
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    ABSTRACT: An analog to digital conversion scheme based on an Asynchronous SigmaDelta Modulator is presented. It uses a Time-to-Digital converter to convert the continuous-time square wave signal produced by the Asynchronous SigmaDelta Modulator to a time-quantized digital signal. The original input signal is then recovered by applying a digital demodulation algorithm derived from general duty-cycle modulation theory. This technique shifts the complexity towards the digital domain and is therefore especially suited for ultra-low voltage technologies beyond 90 nm. Simulations show 13 bit accuracy for Bluetooth baseband 500 kHz with a first-order SigmaDelta modulator and a Time-to-Digital Converter with 10 ps resolution running at 12 MHz. Using a second-order feedback system to shape the quantization noise of the Time-to-Digital converter, the bandwidth can be increased to 12 MHz with 12 bit accuracy, suitable for video applications.
    Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on; 06/2008

Publication Stats

47 Citations
6.72 Total Impact Points

Institutions

  • 2008–2010
    • KU Leuven
      • Department of Electrical Engineering (ESAT)
      Leuven, VLG, Belgium