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    ABSTRACT: This paper describes the key technology to realize high density flash memory, which has quarter-micron Shallow Trench Isolation (STI), Ti-silicided polycrystalline silicon (poly-Si) gate and source/drain, and tungsten (W) local inter-connect sourceline. Extremely small cell size of 0.44 μm<sup>2</sup> has been obtained with 0.25 μm design rule. This cell size is about 30% that of conventional NOR flash cell. To minimize the cell size, the cell gate is patterned with length of 0.25 μm, which can be achieved by using channel erasing scheme. STI and 0.15 μm floating gate separation can realize a 0.55 μm bitline pitch. W sourceline can reduce sourceline resistance and the number of metal sourcelines in the array. In addition, poly-Si gate and active source/drain areas are Ti-silicided at both cells and peripheral transistors, which results in high-speed operation of memory array and peripheral circuits. This high-density NOR cell technology will be essential to realize a low cost and high-performance flash memory and flash embedded logic devices
    Electron Devices Meeting, 1998. IEDM '98 Technical Digest., International; 01/1999