S. Ponoth

Publications (5)0 Total impact

• Conference Proceeding: ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

  K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, B. Haran, A. Kumar, T. Adam, A. Reznicek, N. Loubet, H. He, [......], T. Wu, H. Bu, V. Paruchuri, D. Sadana, V. Narayanan, W. Haensch, J. O'Neill, T. Hook, M. Khare, B. Doris
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  ABSTRACT: For the first time we report extremely thin SOI (ETSOI) CMOS with 22 nm gate length (LG) and sub-100 nm contacted gate pitch for system-on-chip (SoC) applications. Multi-Vt transistors are demonstrated with competitive drive currents (NFET/PFET) of 1150/1050 μA/μm at Ioff = 100 nA/μm for high performance (HP) and 920/880 μA/μm at Ioff = 1 nA/μm for low power (LP), respectively, at VDD = 1 V. High density 6-T SRAM cells down to 0.08 μm2 are demonstrated. Compared with a 28nm bulk LP technology, the high drive currents of ETSOI transistors coupled with large capacitance reduction by aggressive LG scaling result in 25% improvement in ETSOI ring oscillator (RO) speed. Auxiliary ETSOI devices including epitaxy resistors with high precision and gated diodes with near ideal characteristics are fabricated to complete device menu for early ETSOI SoC design.
  VLSI Technology (VLSIT), 2011 Symposium onVLSI Technology (VLSIT), 2011 Symposium on; 01/2011
• Conference Proceeding: Extremely thin SOI (ETSOI) technology: Past, present, and future

  K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, J. Kuss, L.F. Edge, A. Kimball, S. Kanakasabapathy, S. Schmitz, A. Reznicek, [......], P. Jamison, B.S. Haran, Z. Zhu, S. Fan, H. Bu, D.K. Sadana, P. Kozlowski, J. O'Neill, B. Doris, G. Shahidi
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  ABSTRACT: As the mainstream bulk devices face formidable challenges to scale beyond 20nm node, there is an increasingly renewed interest in fully depleted devices for continued CMOS scaling. In this paper, we provide an overview of extremely thin SOI (ETSOI), a viable fully depleted device architecture for future technology. Barriers that prevented ETSOI becoming a mainstream technology in the past are specified and solutions to overcome those barriers are provided.
  SOI Conference (SOI), 2010 IEEE International; 11/2010
• Conference Proceeding: Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

  A. Khakifirooz, K. Cheng, P. Kulkarni, J. Cai, S. Ponoth, J. Kuss, B.S. Haran, A. Kimball, L.F. Edge, A. Reznicek, [......], D. Horak, H. Bu, D.K. Sadana, P. Kozlowski, D. McHerron, J. O'Neill, B. Doris, W. Haensch, E. Leobondung, G. Shahidi
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  ABSTRACT: The authors explored some of the challenges of the extremely thin SOI technology for mainstream CMOS. Faceted RSD was used to minimize parasitic capacitance. PFET performance is competitive with best bulk CMOS technologies, while NFET performance can be increased by further reduction in the series resistance. The impact of silicon thickness on the device variability was studied to quantify wafer uniformity requirement.
  VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on; 05/2010
• Conference Proceeding: Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

  K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, J. Kuss, D. Shahrjerdi, L.F. Edge, A. Kimball, S. Kanakasabapathy, K. Xiu, [......], L.H. Vanamurth, S. Fan, D. Horak, H. Bu, P.J. Oldiges, D.K. Sadana, P. Kozlowski, D. McHerron, J. O'Neill, B. Doris
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  ABSTRACT: We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 ¿A/¿m, respectively, at I_off = 300 pA/¿m, V_DD = 0.9V, and L_G = 25 nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low V_T variability is achieved with A_Vt of 1.25 mV·¿m in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.
  Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
• Conference Proceeding: ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm² SRAM cell

  K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, B. Haran, A. Kumar, T. Adam, A. Reznicek, N. Loubet, H. He, [......], T. Wu, H. Bu, V. Paruchuri, D. Sadana, V. Narayanan, W. Haensch, J. O'Neill, T. Hook, M. Khare, B. Doris
  [show abstract] [hide abstract]
  ABSTRACT: For the first time we report extremely thin SOI (ETSOI) CMOS with 22 nm gate length (L_G) and sub-100 nm contacted gate pitch for system-on-chip (SoC) applications. Multi-V_t transistors are demonstrated with competitive drive currents (NFET/PFET) of 1150/1050 μA/μm at I_off = 100 nA/μm for high performance (HP) and 920/880 μA/μm at I_off = 1 nA/μm for low power (LP), respectively, at V_DD = 1 V. High density 6-T SRAM cells down to 0.08 μm² are demonstrated. Compared with a 28nm bulk LP technology, the high drive currents of ETSOI transistors coupled with large capacitance reduction by aggressive L_G scaling result in 25% improvement in ETSOI ring oscillator (RO) speed. Auxiliary ETSOI devices including epitaxy resistors with high precision and gated diodes with near ideal characteristics are fabricated to complete device menu for early ETSOI SoC design.
  VLSI Circuits (VLSIC), 2011 Symposium on;