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ABSTRACT: Complex chips may today include several Analog-to-Digital and Digital-to-Analog Converters. These modules interface the external analog word with the internal digital computation circuitry such as processor cores. Correct internal digital computation consequently critically depends on high quality conversion even under stringent performance requirements. In order to meet these requirements, the new generations of high speed and resolution ADCs are calibrated after manufacturing. In this paper, we propose an original auto-correction scheme for ADC with an in situ calibration capability able to take into account the specific dynamic and the environment of the application and the aging effects. The scheme is validated through extensive simulations.
Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW), 2010 IEEE 16th International; 07/2010
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ABSTRACT: Standard production test techniques for ADC require an ATE with an arbitrary waveform generator (AWG) with a resolution at least 2 bits higher than the ADC under test resolution. This requirement is a real issue for the new high-performance ADCs. This paper proposes a test solution that relaxes this constraint. The technique allows the test of ADC harmonic distortions using only low-cost ATE. The method involves two steps. The first step, called the learning phase, consists in extracting the harmonic contributions from the AWG. These characteristics are then used during the second step, called the production test, to discriminate the harmonic distortions induced by the ADC under test from the ones created by the generator. Hardware experimentations are presented to validate the proposed approach.
VLSI Design 01/2008; 2008(2):17.
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ABSTRACT: The long and complex procedure to test ADCs constitutes an important issue in the context of mixed-signal testing. To lower the testing costs, we propose shorter but less selective test flows solely based on spectral analysis. This paper investigates the efficiency that can be achieved using this approach and studies the influence of the ADC specifications on the efficiency of the proposed dynamic-only test flows.
Journal of Electronic Testing 05/2005; 21(3):291-298. · 0.47 Impact Factor
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ABSTRACT: Gate Oxide Short (GOS) defects are becoming predominant as technology is scaling down. Boolean and IDDQ testing of this defect has been widely studied but there is no paper dedicated to delay testing of this defect. So, this paper studies the delay behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective of this paper is to give a detailed analysis of the behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance and the GOS location. Because an accurate analysis is desired, the bi-dimensional array will be used. Because a complete analysis is desired, we derive the dynamic characteristic of the GOS as a function of the GOS resistance and location. It is demonstrated that i) GOS has a significant impact on gate delay, ii) GOS located close to the source of the transistor and with small resistance has very high impact.
Journal of Computer Science and Technology 02/2005; 20(2):195-200. · 0.56 Impact Factor
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ABSTRACT: Testing of Analog-to-Digital Converters is classically composed of two successive and independent phases: the histogram-based test technique evaluating static specifications and the spectral analysis technique evaluating the dynamic performances. Consequently, the fundamental objective here is to investigate the feasibility of an alternative test flow involving exclusively spectral analysis to replace these two time consuming and expensive phases. The viability of this solution depends on the ability of spectral analysis to detect static specifications. In this context, this paper presents a new methodology based on a statistical approach to quantitatively evaluate the efficiency of detecting static errors from dynamic parameter measurements. This methodology has been implemented in an in-house automatic tool allowing one to process any ADC specifications. It is then possible to choose a priori the best test flow for a given application.
Journal of Electronic Testing 05/2004; 20(3):257-267. · 0.47 Impact Factor
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ABSTRACT: ADCs are fully characterized by both static and dynamic parameters. Testing methods usually combine a histogram-based approach with a spectral analysis to determine the complete set of ADCs parameters. In the view of a unique test procedure, this paper investigates the correlation between both kinds of parameters. Experimental results demonstrate that under appropriate test conditions, the dynamic parameters extracted from a classical FFT exhibit significant variations against ADC offset, gain and non-linearity errors, opening the way of a low-cost test strategy in the frequency domain.
Journal of Electronic Testing 01/2004; 20(4):375-387. · 0.47 Impact Factor
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ABSTRACT: In the context of analog BIST for ADC, this paper presents two structures for the internal generation of a linear signal used with the histogram-based test technique. All of these structures use wide-swing current mirrors and an original adaptive system to make the generators less sensitive to process variations. The first structure allows us to generate high quality ramp signal. In a second step, a very high accuracy triangle-wave signal generator is presented in order to improve the equivalent linearity of the generated analog test signal.
Journal of Electronic Testing 07/2003; 19(4):469-479. · 0.47 Impact Factor
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ABSTRACT: This paper presents a new model for gate-to-channel GOS defects. The transistors used in digital cell library are usually designed with a minimum-size. This new model permits to handle minimal-length transistors allowing the simulation of GOS defects in realistic digital circuits. Based on the electrical analysis of the defect behavior, a comprehensive method for the model construction is detailed. It is shown that the behavior of the proposed model matches in a satisfactory way the behavior of a defective transistor including the random parameters of the defect.
Journal of Electronic Testing 07/2003; 19(4):377-386. · 0.47 Impact Factor
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ABSTRACT: This paper concerns the test of mixed-signal circuits. A novel DFT approach for analog parts constituted of several op-amp-based modules is presented. The idea is to bring the testability resources (controllability and observability) on the frontier of each embedded module by creating transparent paths between external and local I/O's. The key point of this transformation is to permit each analog stage to have a test mode for which it is converted into a follower stage. Adaptative solutions are proposed depending of the availability of on-chip digital resources eventually re-usable to manage analog test. The testability cost is shown to be very low in terms of additional circuitry, number of extra pins, analog response penalty and test management. A case study is presented that demonstrates the applicability of the method.
Asian Test Symposium. 11/2001;
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ABSTRACT: This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique. An original approach is developed to extract the ADC parameters from the histogram with a minimum area overhead. In particular, it is shown that the choice of a triangle-wave input signal combined with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry.
Journal of Electronic Testing 03/2001; 17(2):139-147. · 0.47 Impact Factor
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ABSTRACT: The histogram method is a very classical test technique for Analog to Digital Converters (ADCs), but only used for external testing because of the large amount of required hardware resources. This paper discusses the viability of a BIST implementation for this technique. An original approach is developed that permits to extract the ADC parameters with a reduced area overhead. This approach involves (i) the calculation of the parameters using approximations and (ii) the decomposition of the global test in a code-after-code test procedure. These two features allow a significant reduction of the required operative resources and memory dedicated to the storage of experimental data. In addition, the use of a piece-wise approximation for computing the ideal histogram also permits to minimize the memory dedicated to the storage of reference data.
Journal of Electronic Testing 01/2001; 17(3):255-266. · 0.47 Impact Factor
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ABSTRACT: This paper aims at defining an efficient test strategy for switched-current circuit testing. Taking into account the specificity of these circuits, we propose an original structural test technique as an alternative to traditionally-used functional verification. This technique is validated both at the cell and block levels. Test results demonstrate that a high fault coverage can be achieved with a low cost test procedure. A mixed strategy combining benefits of functional and structural approaches is derived.
Journal of Electronic Testing 01/2000; 16(3):259-267. · 0.47 Impact Factor
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ABSTRACT: This paper analyzes the possibilities and limitations of defect detection using fault model oriented test sequences. The analysis is conducted through the example of a short defect considering the static voltage test technique. Firstly, the problem of defect excitation and effect propagation is studied. It is shown that the effect can be either a defective effect or a defect-free effect depending on the value of unpredictable parameters. The concept of Analog Detectability Interval (ADI) is used to represent the range of the unpredictable parameters creating a defective effect. It is demonstrated that the ADIs are pattern dependent. New concepts (Global ADI, Covered ADI) are then proposed to optimize the defect detection taking into account the unpredictable parameters. Finally, the ability of a fault oriented test sequence to detect defect is discussed. In particular, it is shown that the test sequence generated to target the stuck-at faults can reasonably guarantee short defect detection till a limit given by the Analog Detectability Intervals.
Journal of Electronic Testing 01/1999; 14(1):13-22. · 0.47 Impact Factor
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ABSTRACT: In this paper a new electrical transistor compact model including a Gate Oxide Short defects is proposed based on a charge sheet model approach. Because this model include Gate Oxide Short defect, it allows to fast simulate realistic digital circuits without any change in the electrical simulation netlist. The basic equations and the topology of the model are presented in details using a charge sheet approach. It is demonstrated that the electrical behavior of the proposed model matches in a satisfactory way the defective transistor behavior. Abstract In this paper a new electrical transistor compact model including a Gate Oxide Short defects is proposed based on a charge sheet model approach. Because this model include Gate Oxide Short defect, it allows to fast simulate realistic digital circuits without any change in the electrical simulation netlist. The basic equations and the topology of the model are presented in details using a charge sheet approach. It is demonstrated that the electrical behavior of the proposed model matches in a satisfactory way the defective transistor behavior.
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ABSTRACT: Full characterization of ADC requires both a histogram-based approach and a spectral analysis to determine respectively static and dynamic parameters. This paper investigates whether static performances can be extracted from spectral analysis, in order to develop a low-cost test procedure. Results show that under appropriate test conditions, the dynamic parameters extracted from a classical FFT exhibit significant variations against ADC offset and gain errors.
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ABSTRACT: This paper associates a new enhanced spectral analysis procedure with a binning test strategy to propose an optimal ADC test flow. This test flow achieves the same selectivity of faulty and fault free devices than a classical test flow but in a significantly shorter time.
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ABSTRACT: This paper presents a technique allowing the test of ADC harmonic distortions with only low-cost ATE. Contrary to a classical DSP-based test that requires an arbitrary wave generator (AWG) on the ATE with a resolution at least 2 bit higher than the ADC under test, the proposed solution permits to test ADCs using same resolution AWG. The method involves an initial learning phase in which the characteristics of the AWG are extracted. These characteristics are then used during production test to discriminate the harmonic distortions induced by the ADC under test from the ones induced by the generator. Hardware experimentations are presented to validate the proposed approach.
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ABSTRACT: This paper studies the voltage and current behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective of this paper is to give a detailed analysis of the behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance, the GOS location and the GOS size. Because an accurate analysis is desired, the bi-dimensional array will be used. Because a complete analysis is desired, we derive characteristic of the GOS as a function of the GOS resistance, location and size. Finally, because a realistic analysis is desired the model has been validated through measurements of GOS intentionally injected into a designed and manufactured circuit.
IEEE International Test Conference (TC)
