C.H. Diaz,
K. Goto,
H.T. Huang,
Yu. Yasuda,
C.P. Tsao,
T.T. Chu,
W.T. Lu,
V. Chang,
Y.T. Hou,
Y.S. Chao, [......], K.B. Thei,
C.H. Lee,
S.H. Yang,
J.Y. Cheng,
K.T. Huang,
J.J. Liaw,
Y. Ku,
S.M. Jang,
H. Chuang,
M.S. Liang
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ABSTRACT: A 32 nm gate-first high-k/metal-gate technology is demonstrated with the strongest performance reported to date to the best of our knowledge. Drive currents of 1340/940 muA/mum (n/p) are achieved at I<sub>off</sub>=100 nA/mum, V<sub>dd</sub>=1 V, 30 nm physical gate length and 130 nm gate pitch. This technology also provides a high-Vt solution for high-performance low-power applications with its high drive currents of 1020/700 muA/mum (n/p) at total I<sub>off</sub> ~1 nA/mum @ V<sub>dd</sub> = 1V. Low sub-threshold leakage was achieved while successfully containing I<sub>boff</sub> and I<sub>goff</sub> well below 1 nA/um. Ultra high density 0.15 um<sup>2</sup> SRAM cell is fabricated by high NA 193 nm immersion lithography. Functional 2 Mb SRAM test-chip in 32 nm design rule has been demonstrated with a controllable manufacturing window.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
