H. Yoshida,
T. Toyoda,
T. Yasuda,
Y. Ogasawara,
M. Ishii,
T. Murasaki,
G. Takemura,
M. Iwanaga,
T. Takida,
Y. Araki, [......],
R. Ito,
H. Okuni,
T. Kato, K. Sato,
K. Nonin,
K. Osawa,
R. Fujimoto,
S. Kawaguchi,
H. Tsurumi,
N. Itoh
[show abstract]
[hide abstract]
ABSTRACT: In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (high speed uplink packet access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (analog base-band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (high speed downlink packet access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (digital base-band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312 MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (high speed packet access) and GSM/EDGE.
Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European; 10/2008
