A.K. Kapoor,
W. Zhang,
S. Sonkusale,
Y. Liu, P. Gregory,
U.C. Sridharan,
C. Stager,
N. Eib,
Z. Xie,
M. Vora,
J. Prasad,
D. Thummalapally,
R. Chou
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ABSTRACT: Digital logic based on nanoscale complementary junction field effect transistors in silicon is reported in order to address scaling issues with CMOS. For the first time, complementary logic based on an enhancement mode JFET (cJFET), consisting of n- and p-channel JFET transistors built on bulk silicon and SOI with 60 nm gate length operating at 0.5 V has been demonstrated. Scalability of this technology has been confirmed by simulation of JFET devices with channel length equal to 16 nm.
Electronics Letters 06/2010; · 0.96 Impact Factor
