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Publications (13)4.91 Total impact

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    ABSTRACT: In this paper, we present the evaluation results of low cure temperature (less than 200$^{\circ}{\rm C}$) dielectric materials (LCTDMs) in terms of processability and adhesion to silicon nitride and mold compound substrates. The results showed that the LCTDMs have good adhesion to the above substrates. Integration of thin-film passives such as inductors, capacitors, and band-pass filters were also demonstrated on mold compound wafer platform using electroplated copper (Cu) and LCTDM. Thin-film passives fabricated on the mold compound platform using LCTDM showed better performance by two times when compared to the passives fabricated on a high-resistivity silicon wafer. Reliability test vehicles of multichip embedded micro-wafer-level package (EMWLP) were fabricated using Cu redistribution line (RDL), LCTDM, and electroplated Cu under bump metallization with lead-free (Pb-free) solder bump interconnects. Test vehicles were subjected to various package-level and board-level reliability tests as per the JEDEC standards, and failure analysis was carried out after reliability tests. EMWLP with LCTDM passed package-level reliability tests such as unbiased highly accelerated stress test, thermal cycling (TC), and moisture sensitivity test level 3. Test vehicles with underfill passed board-level TC and drop tests. A complete description of dielectric material evaluation for EMWLP, process development of thin-film passives fabrication, and multilayer RDL integration on reconfigured mold compound wafer and its reliability results are discussed.
    IEEE Transactions on Components, Packaging, and Manufacturing Technology 01/2012; 2(1). · 1.26 Impact Factor
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    ABSTRACT: The continuous push for smaller bump pitch interconnection in line with smaller Cu/low- k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low- k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low- k test chip on flip chip ball grid array (FCBGA) package. The Cu/low- k chip is a 65-nm nine-metal layer chip with 150-μm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.
    IEEE Transactions on Components, Packaging, and Manufacturing Technology 06/2011; · 1.26 Impact Factor
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    ABSTRACT: A simple and novel design, integrating discrete commercial micro-lens and vertical illuminated optoelectronic component in a substrate with high accuracy, is presented here. Without affecting the optical performances, this integrated optical carrier also allows high-frequency radio-frequency interconnects. This feature is critical for high-speed operation. The high accuracy integrated optical carrier improves the optical coupling efficiency and helps to relax the tight circuit assembly tolerance requirement. The integrated optical carrier can be used for various photonic applications which employ vertical illuminated optoelectronic components. An integrated optical carrier prototype is designed here for the optical electrical interconnect printed circuit board (OECB). For this OECB design, the simulated results show that the integrated optical carrier helps to give an assembly misalignment tolerance of more than ±20 μm with an increase of 1 dB coupling loss. In addition, the simulated optical insertion loss from the transmitter to the receiver is less than 1.4 dB. The optical performance of the prototype integrated optical carrier is measured and compared with the simulation results to ascertain the design concept. For different OECB waveguide designs, dimensions and positions, this integrated optical carrier design is amended to give a better performance and misalignment tolerance.
    IEEE Transactions on Components, Packaging, and Manufacturing Technology 02/2011; · 1.26 Impact Factor
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    ABSTRACT: In recent years, embedded wafer level package (EMWLP) technology has become a promising platform for SiP integration [1] due to its relatively low cost and good electrical performance [1–2]. As the platform is being considered for higher frequency applications (eg. 77-GHz radar), it becomes pertinent to characterize for the dielectric properties of the materials involved. Another concern is that the dielectric properties of inhomogeneous materials (eg. mold compound) may vary from batch to batch. Thus, it is desirable to have structures which are compact to enable in-situ dielectric characterization. In this work, we propose meander T-resonator structure for in-situ dielectric characterization. We also attempt to extract for the relative permittivity of the mold compound in a coplanar waveguide (CPW) configuration, based on analytical expressions. Lastly, we compare the results extracted from both the T-resonator and transmission line (TL) structure.
    01/2011;
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    ABSTRACT: Large core step-index plastic optical fibers (SI-POF) are bandwidth limited due to their high modal dispersion and coupling loss at the receiver. To date, the large core SI-POF are typically deployed up to 150 Mb/s applications. This paper reports the transmission of 2.5 Gb/s on 980 μm core step-index plastic optical fiber with fiber-based mode conditioning elements that are part of the connector assembly. The built-in mode conditioners are tapered fiber tips that provide restricted mode launching at transmitter and mode filtering at the receiver side. The structures, at the tip of POF, are optimized by optical simulations and fabricated using laser fusion process. The connector assembly is realized by precisely encapsulating the mode conditioners with a metallic ferrule and positioned using optical grade epoxies. These plug-in modules are inserted to a typical SFP transceiver LC connector receptacle and characterized for gigabit rates.
    IEEE Transactions on Advanced Packaging 12/2010; · 1.12 Impact Factor
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    ABSTRACT: This paper discusses wafer level vacuum sealing technology with evaporated AuSn solder for a microelectromechanical systems (MEMS) resonator without getter material. The MEMS resonator is fabricated and characterized in a vacuum chamber. Relationship between the Q-factor of the MEMS resonator and the vacuum level is established and used as a reference for later vacuum level calibration. Wafer bonding using evaporated AuSn solder is performed in an EVG wafer bonder. With optimized bonding conditions, the achieved shear strength is higher than 59 MPa and uniform cross-section of the bonding ring has been achieved. The calculated He leakage rate is between 10<sup>−13</sup> atm cc/s and 10<sup>−14</sup> atm cc/s. By comparing the measured Q-factor of packaged resonator with the reference curve, the corresponding vacuum level is 0.2 Torr. Reliability tests results show that shear strength decreases for 7% and still high enough for real application. The vacuum level after reliability tests is comparable to that of long term vacuum level.
    Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th; 07/2010
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    ABSTRACT: In this paper, the effect of TSV (Through Silicon Via) parameters on the equivalent thermal conductivity of TSV interposer and the effect of the TSV interposer on the thermal performance of the package have been elaborated. The modeling approach using in this paper includes compact modeling for the package and detailed modeling for the TSV interposer. The objective of compact modeling is to study the effect of TSV interposer on thermal performance of the package, while the objective of detailed modeling is to extract the equivalent thermal conductivity of TSV interposer which is used for compact modeling. The proposed package in this study includes a large die with fine pitch, a silicon interposer with TSV, a 1-2-1 buildup substrate and a PCB board. In addition, to evaluate the thermal performance of the proposed package, a similar package without the TSV interposer is also modeled in this study for comparison. The results of detailed modeling show that the equivalent thermal conductivity of TSV interposer can be increased by reducing the pitch and via ratio of TSV, as well as increasing the plating thickness of partial filled TSV and using highly conductive filler material. Furthermore, the results of compact modeling reveal that the proposed TSV interposer improves the thermal performance of the package. The thermal resistance of the package decreases when the interposer size and thickness increase, and the equivalent thermal conductivity of TSV interposer has negligible effect on thermal performance of the package.
    Electronics Packaging Technology Conference, 2009. EPTC '09. 11th; 01/2010
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    ABSTRACT: In this paper, through silicon via (TSV) based interposer fabrication processes for 3D stack packaging has been presented. An interposer test chip of 25 × 25 mm size, has been designed with full array TSVs of 50 um size vias at 300 um pitch. TSVs of aspect ratio 4 are formed on 8 inch wafer using DRIE process and these vias are isolated by thermal oxide, followed by barrier/seed layer of Ti/Cu deposition. TSVs are filled with solid copper (Cu) using optimized pulse reverse damascene electroplating and Cu chemical mechanical polishing (CMP) process also developed to remove the over burden copper with minimum dishing. Multi layer front side metallization process has been demonstrated using electroplated Cu as re-distribution layers (RDL) and spin-on-dielectrics as RDL passivation. Solid Cu filled TSVs are exposed at the backside of the TSVs using backgrinding and Cu CMP. Thin wafer handling process was developed for backside metallization on 200 um thick interposer wafers using support wafer with temporary adhesive bonding. Low temperature dielectric process has been optimized for backside via passivation to isolate the vias from surrounding silicon and backside RDL process as temporary adhesive can not withstand for high temperature processes. The support wafer is de-bonded by sliding at high temperature, followed by cleaning of temporary adhesive material on the front side of interposer wafer using cleaning chemical. TSV interposer of 200 um thickness has been fabricated successfully and the vias are in very good connectivity from the top to the bottom. Complete interposer fabrication process issues and solutions have been discussed.
    Electronics Packaging Technology Conference, 2009. EPTC '09. 11th; 01/2010
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    ABSTRACT: Die stacking is widely adopted for high chip count systems to reduce the requirement of substrate area. The incorporation of Through-Silicon-Via (TSV) as vertical interconnects further reduces the interconnect path length from the top die to substrate. As the fabrication resolution keeps on shrinking, devices of even higher chip count are required to be assembled in a single package, which results in even longer 3D interconnects. As such, accurate modelling of high speed interconnects is essential for the high frequency systems. In this work, D modelling and Full wave EM simulation were performed on the interconnect path which consists of TSV, metal re-distribution Layer (RDL) and bumps. Effect of the different number of die stack was analyzed based on the simulation results.
    01/2010;
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    ABSTRACT: Thermal management in 3D packaging is a critical factor to be considered in enabling this technology to be exploited further. Heat density in excess of 100 W/cm<sup>2</sup> can be achieved due to the smaller footprint of such packages. Liquid cooling through microchannels embedded within the package had been shown to improve the thermal characteristics of packages. In this work, a liquid cooling solution is designed with emphasis on the flow distribution through the microchannels. The use of a reducing plenum design had been shown to lower the pressure drop requirement while improving the thermal characteristics. The thermal implication with achieving deep channels through the DRIE process is an introduction of a significant thermal resistance to the overall thermal network. Numerical modeling of the actual physical components in the cooling module had also being done to evaluate the system operating points and hence sizing the pump. The approach taken in this work identified the issues faced when embedding heat transfer features within the package and in a cooling solution. The system modeling had also been shown to provide a good estimate of the operating conditions within the physical module.
    Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th; 01/2009
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    ABSTRACT: A dry film photoresist was selected as the sacrificial material for a metal lift off process. However, a weak and inconsistent adhesion of the evaporated under bump metallurgy (UBM) and solder on the passivation surface was observed during the dry film stripping process. This problem may be due to the poor negative profile (88 to 89 degrees) of the patterned dry film side wall after dry film developing, resulting to inconsistent metal lift off. A few dry film predevelopment and post development parameters are identified and tested from the standard dry film development process, to obtain a negative profile of the dry film to be less than 84 degrees. After each test, cross section of the patterned dry film side wall is observed under a microscope to check if a negative profile is obtained. The 50 ¿m thick dry film at 35 mJ/cm2 with other modifications of the process gives the best results.
    01/2009;
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    ABSTRACT: In this paper, we have developed the evaluation results of low cure temperature (less than 200 deg C) dielectric materials in terms of process ability and adhesion on SiN and mold compound substrates. The results showed that the low cure temperature dielectric materials have good adhesion on SiN and mold compound substrate. Integration of thin film passives like inductors, capacitors and band pass filters are also demonstrated on this mold compound wafer platform using electroplated Cu and low cure temperature dielectric material. Developed thin film passives on mold compound wafer platform have significantly improved the passives performances that are benchmarked against high resistivity silicon wafer (HiRSi). Reliability test vehicles are fabricated using Cu RDL, low cure temperature dielectric material and electroplated Cu UBM with SAC solder bump interconnects. A complete description of dielectric material evaluation for EMWLP, process development of thin film passive fabrication and multi-layer RDL integration on reconstructed mold compound wafer has been discussed.
    01/2009;
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    ABSTRACT: This paper presents the assembly optimization and characterization of through-silicon vias (TSV) interposer technology for two 8 �? 10mm2 micro-bumped chips. The two micro-bumped chips represent different functional dies in a system-in-package (SiP). In the final test vehicle, one of the micro-bumped chips had 100¿m bump pitch and 1,124 I/O; the other micro-bumped chip had 50¿m bump pitch and 13,413 I/O. The TSV interposer size is 25 �? 25 �? 0.3mm3 with CuNiAu as UBM on the top side and SnAgCu bumps on the underside. The conventional substrate size is 45 �? 45mm2 with 1-2-1 layer configuration, a ball-grid array (BGA) of 1mm pitch and a core thickness of 0.8mm. The final test vehicle was subjected to MSL3 and TC reliability assessment. The objective of this paper was to incorporate two 8 �? 10mm2 micro-bumped chips into TSV interposer. The micro-bumped chips should have no underfill voiding issue and the whole package should be able to pass moisture sensitivity level 3 (MSL3) and thermal cycling (TC) reliability assessment. To achieve this objective of incorporating micro-bumped chips into the TSV interposer, the challenges were small standoff height/ low bump pitch of the micro-bumped chip, underfill flowability and its reliability performance. To overcome these challenges, different types of capillary flow underfill, bump layout designs and bump types were evaluated and a quick reliability assessment was used to select the materials and test vehicle parameters for final assembly and reliability assessment.
    01/2009;