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ABSTRACT: This paper studies the elastic deformation field in lattice-mismatched Ge-Si core-shell nanowires (NWs). Infinite wires with
a cylindrical cross section under the assumption of translational symmetry are considered. The strain distributions are found
by minimizing the elastic energy per unit cell using finite element method. This paper finds that the trace of the strain
is discontinuous with a simple, almost piecewise variation between core and shell, whereas the individual components of the
strain can exhibit complex variations. The simulation results are prerequisite of strained band structure calculation, and
pave a way for further investigation of strain effect on the related transport property simulation.
Frontiers of Electrical and Electronic Engineering in China 04/2012; 4(3):342-347.
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ABSTRACT: Intrinsic parameter fluctuations introduced by process variations, such as line edge roughness (LER), create an increasing challenge to the CMOS technology scaling. In this paper, variations in double-gate dopant-segregate Schottky (DSS) MOSFETs, caused by LER of silicon-fin, are systematically investigated using statistical technology computer-aided design simulations. The impact of LER on both Schottky barrier and DSS-MOSFETs are examined contrastively. The results show that DSS-MOSFETs offer a larger and more uniform drive current, but suffer a more serious V t fluctuation. The cause of such larger V t flutuation is also analyzed, thus providing a good starting point to propose way to solve this problem.
IEEE Transactions on Nanotechnology 04/2011; · 2.29 Impact Factor
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ABSTRACT: The strain distribution and strained valence band structure in silicon nanowire with varied thicknesses and deposition temperatures of gate dielectric are discussed in detail in this work. Our calculation indicates that valence subbands are dependent on the structure and process parameters. Strain has little effects in (001) orientation. But in Si (110) nanowire, the valence subbands shift upper and warp remarkably as the gate dielectric becomes thicker. Taking thermal residual strain into consideration, the strained valence subbands go to higher energy positions compared to NW without the residual strain. The different deposition temperature by a certain process slightly influences the valence bands. Strain effects on densities of states and effective masses are also investigated.
Simulation of Semiconductor Processes and Devices, 2009. SISPAD '09. International Conference on; 10/2009
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ABSTRACT: We evaluate the performance of GaAs-GaP core-shell (C-S)-nanowire (NW) field-effect transistors by employing a semiclassical ballistic transport model. The valence-band structures of GaAs-GaP C-S NWs are calculated by using a kldrp method including the strain effect. The calculations show that the strain causes substantial band warping and pushes valence subbands to move up. We demonstrate that the on current can be enhanced with the strength of strain induced in the core, but an extremely thin equivalent oxide thickness may suppress the effect of the strain-induced current improvement. The achieved results can provide a design guide for optimizing device performance.
IEEE Transactions on Electron Devices 07/2009; · 2.32 Impact Factor
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ABSTRACT: The impact of line-edge roughness (LER) on double-gate (DG) Schottky-barrier field-effect transistors (SBFETs) in the level of device and circuit was investigated by a statistical simulation. The LER sequence is statistically generated by a Fourier analysis of the power spectrum of the Gaussian autocorrelation function. The results show that SBFETs are more sensitive to the LER effect in the high- V <sub>gs</sub> region and less sensitive in the subthreshold region compared with DG FinFETs. The aggressive fluctuation of drive current can be attributed to the variation of tunneling barrier width. Lowering the Schottky-barrier height and increasing the silicon-body thickness can suppress the parameter fluctuations from the LER effect. The simulation also shows that a 6T SRAM cell consisting of SBFETs is more vulnerable to noise disturbance than its counterpart consisting of FinFETs, particularly for the read operation, which is due to a larger mismatch of drivability of SBFETs within the cell.
IEEE Transactions on Electron Devices 07/2009; · 2.32 Impact Factor
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ABSTRACT: 3D mixed-mode device-circuit simulation is presented to investigate the impact of line edge roughness (LER) on the stability of a FinFET SRAM. In this work, LER sequence is statistically generated by a Fourier analysis of the power spectrum of Gaussian autocorrelation function. The sensitivity of 20 nm FinFET SRAM of Read and Write static noise margins (SNM) to fin LER is evaluated. The results show that FinFET SRAM is more tolerant of disturbance in write operation than in read disturbance. The dependence of Read SNM on fin LER's root mean square (RMS) amplitude, fin thickness and supply voltage is also analyzed. Furthermore, methods to reduce the LER effect on the FinFET SRAM's read stability are introduced. Optimization of the cell ratio by a multiple-fin design, control of the access transistor's gate bias voltage and replacement of a 6T cell with an 8T cell are possible solutions to continue the scaling trend of SRAM in the nanoscale CMOS technology.
Semiconductor Science and Technology 12/2008; 24(2):025005. · 1.72 Impact Factor
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ABSTRACT: Intra-die fluctuations in the nanoscale CMOS technology emerge inherently to geometrical variations such as line edge roughness (LER) and oxide thickness fluctuations (OTF). A full 3-D statistical simulation is presented to investigate the impact of geometrical variations on the FinFETs performance. In this work, roughness is introduced by a Fourier analysis of the power spectrum of Gaussian autocorrelation function. The influence of different geometrical variation sources is compared and summarized. The results shows that FinFETs performance is most sensitive to the fin LER, which causes a remarkable shift and fluctuations in threshold voltage, drain induced barrier lower effect (DIBL) and leakage current. The impact of gate LER follows that of fin LER. The simulation also suggests quantum confinement effect accounts for the aggressive fluctuations due to fin LER.
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on; 11/2008
