Yuning Zhao

Peking University, Peping, Beijing, China

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Publications (13)10.66 Total impact

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    ABSTRACT: Intrinsic parameter fluctuations introduced by process variations, such as line edge roughness (LER), create an increasing challenge to the CMOS technology scaling. In this paper, variations in double-gate dopant-segregate Schottky (DSS) MOSFETs, caused by LER of silicon-fin, are systematically investigated using statistical technology computer-aided design simulations. The impact of LER on both Schottky barrier and DSS-MOSFETs are examined contrastively. The results show that DSS-MOSFETs offer a larger and more uniform drive current, but suffer a more serious V t fluctuation. The cause of such larger V t flutuation is also analyzed, thus providing a good starting point to propose way to solve this problem.
    IEEE Transactions on Nanotechnology 04/2011; 10(2-10):244 - 249. DOI:10.1109/TNANO.2009.2037222 · 1.62 Impact Factor
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    ABSTRACT: Various Si1-xGex shell strains induced by changing the thickness or tuning the Ge and Si contents as well as by modulating the valence band structure and hole transport characteristics of core/shell nanowire field effect transistors (FETs) have been calculated. As Si1-xGex shell thickness increases, the strained valence subbands shift upwards and warp markedly. Most of the corresponding hole effective masses of the top five subbands decrease. Meanwhile, the hole mobility of the Ge(110) nanowire increases with increasing shell thickness. As the Ge concentration in the Si1-xGex shell decreases, the strained valence subbands and hole mobility show similar shifts. As a result, our calculation indicates the possibility of improving the nanowire performance of heterostructure nanowire FETs.
    Japanese Journal of Applied Physics 04/2010; 49. DOI:10.1143/JJAP.49.04DN01 · 1.06 Impact Factor
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    ABSTRACT: The strain distribution and strained valence band structure in silicon nanowire with varied thicknesses and deposition temperatures of gate dielectric are discussed in detail in this work. Our calculation indicates that valence subbands are dependent on the structure and process parameters. Strain has little effects in (001) orientation. But in Si (110) nanowire, the valence subbands shift upper and warp remarkably as the gate dielectric becomes thicker. Taking thermal residual strain into consideration, the strained valence subbands go to higher energy positions compared to NW without the residual strain. The different deposition temperature by a certain process slightly influences the valence bands. Strain effects on densities of states and effective masses are also investigated.
    Simulation of Semiconductor Processes and Devices, 2009. SISPAD '09. International Conference on; 10/2009
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    ABSTRACT: This paper studies the elastic deformation field in lattice-mismatched Ge-Si core-shell nanowires (NWs). Infinite wires with a cylindrical cross section under the assumption of translational symmetry are considered. The strain distributions are found by minimizing the elastic energy per unit cell using finite element method. This paper finds that the trace of the strain is discontinuous with a simple, almost piecewise variation between core and shell, whereas the individual components of the strain can exhibit complex variations. The simulation results are prerequisite of strained band structure calculation, and pave a way for further investigation of strain effect on the related transport property simulation.
    Frontiers of Electrical and Electronic Engineering in China 09/2009; 4(3):342-347. DOI:10.1007/s11460-009-0050-x
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    ABSTRACT: We evaluate the performance of GaAs-GaP core-shell (C-S)-nanowire (NW) field-effect transistors by employing a semiclassical ballistic transport model. The valence-band structures of GaAs-GaP C-S NWs are calculated by using a kldrp method including the strain effect. The calculations show that the strain causes substantial band warping and pushes valence subbands to move up. We demonstrate that the on current can be enhanced with the strength of strain induced in the core, but an extremely thin equivalent oxide thickness may suppress the effect of the strain-induced current improvement. The achieved results can provide a design guide for optimizing device performance.
    IEEE Transactions on Electron Devices 07/2009; DOI:10.1109/TED.2009.2019739 · 2.36 Impact Factor
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    ABSTRACT: The impact of line-edge roughness (LER) on double-gate (DG) Schottky-barrier field-effect transistors (SBFETs) in the level of device and circuit was investigated by a statistical simulation. The LER sequence is statistically generated by a Fourier analysis of the power spectrum of the Gaussian autocorrelation function. The results show that SBFETs are more sensitive to the LER effect in the high- V <sub>gs</sub> region and less sensitive in the subthreshold region compared with DG FinFETs. The aggressive fluctuation of drive current can be attributed to the variation of tunneling barrier width. Lowering the Schottky-barrier height and increasing the silicon-body thickness can suppress the parameter fluctuations from the LER effect. The simulation also shows that a 6T SRAM cell consisting of SBFETs is more vulnerable to noise disturbance than its counterpart consisting of FinFETs, particularly for the read operation, which is due to a larger mismatch of drivability of SBFETs within the cell.
    IEEE Transactions on Electron Devices 07/2009; DOI:10.1109/TED.2009.2017644 · 2.36 Impact Factor
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    ABSTRACT: Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin field effect transistors (FinFETs) with optimized fin-thickness (T(si)) to reduce the fin line edge roughness (LER) effect both in the device and circuit level. The results show that ultrathin fin will lead to intolerable parameter fluctuations in 20 nm double-gate (DG) FinFETs and FinFETs static random access memory (SRAM). Increasing T(si) can alleviate fin LER effect, but in the meantime it will exacerbate the short channel effect (SCE). TG structure can strengthen the gate controllability over the channel, thus, can suppress SCE and reduce LER effect as well. Adopting TG structure can relax the constraint of fin-thickness to half the gate length. (C) 2009 The Japan Society of Applied Physics
    Japanese Journal of Applied Physics 04/2009; 48(4). DOI:10.1143/JJAP.48.04C052 · 1.06 Impact Factor
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    ABSTRACT: For the radial boundary force induced in the process, the strain energy distribution and strain tensor components in Ge (110) nanowire (NW) are calculated by finite element method. Based on the strain distribution, we compute valence band structures with different radial forces. As increasing force values, top valence subbands shift downwards. The influence on the corresponding effective masses and density of states are also investigated.
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    ABSTRACT: 3D mixed-mode device-circuit simulation is presented to investigate the impact of line edge roughness (LER) on the stability of a FinFET SRAM. In this work, LER sequence is statistically generated by a Fourier analysis of the power spectrum of Gaussian autocorrelation function. The sensitivity of 20 nm FinFET SRAM of Read and Write static noise margins (SNM) to fin LER is evaluated. The results show that FinFET SRAM is more tolerant of disturbance in write operation than in read disturbance. The dependence of Read SNM on fin LER's root mean square (RMS) amplitude, fin thickness and supply voltage is also analyzed. Furthermore, methods to reduce the LER effect on the FinFET SRAM's read stability are introduced. Optimization of the cell ratio by a multiple-fin design, control of the access transistor's gate bias voltage and replacement of a 6T cell with an 8T cell are possible solutions to continue the scaling trend of SRAM in the nanoscale CMOS technology.
    Semiconductor Science and Technology 12/2008; 24(2):025005. DOI:10.1088/0268-1242/24/2/025005 · 2.21 Impact Factor
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    ABSTRACT: Intra-die fluctuations in the nanoscale CMOS technology emerge inherently to geometrical variations such as line edge roughness (LER) and oxide thickness fluctuations (OTF). A full 3-D statistical simulation is presented to investigate the impact of geometrical variations on the FinFETs performance. In this work, roughness is introduced by a Fourier analysis of the power spectrum of Gaussian autocorrelation function. The influence of different geometrical variation sources is compared and summarized. The results shows that FinFETs performance is most sensitive to the fin LER, which causes a remarkable shift and fluctuations in threshold voltage, drain induced barrier lower effect (DIBL) and leakage current. The impact of gate LER follows that of fin LER. The simulation also suggests quantum confinement effect accounts for the aggressive fluctuations due to fin LER.
    Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on; 11/2008
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    ABSTRACT: 3-D mixed-mode device-circuit simulation is presented to investigate stochastic mismatch of FinFETs SRAM cell induced by process variation including fin-thickness and gate length variation as well as fin line edge roughness (LER). In this work, 20 nm FinFETs SRAMpsilas sensitivity of read and write static noise margin (SNM) to process variation is evaluated. The worst cases of read and write SNM under the influence of process variation are summarized. The results show that FinFETs SRAMpsilas stability is most sensitive to the access transistorpsilas fin-thickness variation. Under the worst cases, increasing the pull-down transistorpsilas fin-number may improve read SNM. The fin LER can cause aggressive fluctuations of the butterfly-curves and impose a big challenge on robust FinFETs SRAM design. Adopting 8T cell instead of 6T cell can alleviate the fin LER effect on read stability.
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    ABSTRACT: Summary form only given. Through full 3D simulation, we evaluate the impact of gate LER mainly focuses on device parameters including SS, DIBL and Ioff. The variation of the device performance increases when rms amplitude or correlation length increases. Also our results show that gate LER become an urgent issue when the channel length decreases into sub-30nm.
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    ABSTRACT: We evaluate the performance of GaAs-GaP core-shell nanowire field effect transistors by employing a semiclassical ballistic transport model and a k·p calculation of the valence band structures including the strain effect. We find that the strain will induce substantial modulation on the nanowire valence band structures and this modulation will push more conduction channels into the bias window as the shell thickness increases. We analyze its impact on the transistor performance, and our simulation results indicate that in order to achieve a good ON/OFF current ratio the epitaxial shell should be grown thin enough.