Wandong Kim

Seoul National University, Seoul, Seoul, South Korea

Are you Wandong Kim?

Claim your profile

Publications (22)20.06 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: In this study, the gate-all-around (GAA) poly-Si channel flash memories with a nitride charge trap layer (Si<sub align="right"> 3 </sub>N<sub align="right"> 4 </sub>) have been successfully fabricated. Electrical characteristics of fabricated devices including the threshold voltage shift with program/erase operation have been investigated. Gate structures were formed differently according to each defined channel width. Results show that devices with the gate-all-around structure have superior program efficiency. To investigate the effect of gate structure on the program efficiency, TCAD simulation was carried out. Another issue of the fabricated devices is poor erase operation due to the quality of the blocking oxide. This issue has been studied through the capacitor composed of the same stack structure, and the way to improve the erase operation has been proposed.
    11/2013; 11(1/2/3/4).
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this study, the gate-all-around (GAA) poly-Si channel flash memories with charge trap layer (Si3N4) have been successfully fabricated. Electric characteristics of fabricated devices including threshold voltage shift with program/erase operation have been investigated. Gate configurations were structured differently according to each defined channel width. Results show that devices with gate-all-around structure have superior program efficiency. To investigate the effect of gate configuration on the program efficiency, TCAD simulation was carried out.
    Nanoelectronics Conference (INEC), 2013 IEEE 5th International; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this study, we investigate the variation of threshold voltage and ON-cell current caused by cell gate length fluctuation in silicon--oxide--nitride--oxide--silicon (SONOS) NAND flash memory with virtual source and drain (VSD). The fluctuation in cell gate length caused by process errors such as line edge roughness, etch slope variation, and lithography resolution-induced error affects threshold voltage and ON-cell current considerably. Our results show that three-dimensional (3D) structures have robust immunity to the cell gate length fluctuation effect. From the viewpoint of array design, threshold voltage and ON-cell current variation due to cell gate length fluctuation can be reasonably mitigated by enlarging the cell gate length in a word line (WL) pitch and reducing the body doping concentration. In addition, the tendency of the variation by technology node scaling and the comparison with the junctionless NAND flash memory structure are also investigated.
    Japanese Journal of Applied Physics 07/2012; 51(7):4301-. · 1.07 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Various critical issues related with 3-D stacked nand Flash memory are examined in this paper. Our single-crystalline STacked ARray (STAR) has many advantages such as better scalability, possibility of single-crystal channel, less sensitivity to 3-D interference, stable virtual source/drain characteristic, and more extendability over other stacked structures. With STAR, we proposed a unit 3-D structure, i.e., “building.” Then, using this new component, 3-D block and full chip architecture are successfully designed. For the first time, the structure and operation methods of the “full” array are considered. The fully designed 3-D nand Flash architecture will be the novel solution of reliable 3-D stacked nand Flash memory for terabit density.
    IEEE Transactions on Electron Devices 01/2012; 59(1):35-45. · 2.06 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory array by using TCAD simulation. Also, we compare the cell characteristics of NAND flash with different structures, gate-all-around (GAA) and double gate (DG).
    Silicon Nanoelectronics Workshop (SNW), 2012 IEEE; 01/2012
  • [Show abstract] [Hide abstract]
    ABSTRACT: A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that has a cut-off gate and two memory nodes at a single wordline. To increase the density of the GTB memory integration, we stacked poly-silicon gates in a vertical direction. In a 4F$^2$ size, we can integrate 2 N memory nodes, where N is the number of stacked gates. In this paper, its fabrication method is introduced and electrical characteristics are investigated thoroughly by device simulations.
    IEEE Transactions on Nanotechnology 01/2012; 11(2):307-313. · 1.80 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: We propose a new three-dimensional (3D) NAND flash memory array having Tied Bit-line and Ground Select Transistor (TiGer) [1]. Channels are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked channels, a novel operation scheme is introduced instead of adding supplementary control gates. The stacked layers are selected by using ground select line (GSL) and common source line (CSL). Device structure and fabrication process are described. Operation scheme and simulation results for program inhibition are also discussed.
    IEICE Transactions on Electronics. 01/2012; E95.C(5):837-841.
  • [Show abstract] [Hide abstract]
    ABSTRACT: For the first time, a comprehensive study is done regarding the stability under simultaneous application of light and gate dc bias in amorphous hafnium-indium-zinc-oxide (α-HIZO) thin-film transistors (TFTs). Subthreshold swing (SS) degradation, a negative threshold voltage (V<sub>th</sub>) shift, and the occurrence of hump are observed in transfer curves after applying a negative gate bias and light stress. Based on the retention test at room temperature and the hysteresis analysis, it is revealed that all these phenomena result from hole trapping in the gate insulator. Moreover, it is proven that the SS degradation and hump occurrence are mainly attributed to hole trapping in SiO<sub>2</sub> at the edge regions along the channel length/width directions and that a negative V<sub>th</sub> shift is derived from hole trapping in the gate insulator far from the SiO<sub>2</sub>/HIZO interface.
    IEEE Transactions on Electron Devices 05/2011; · 2.06 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this letter, a novel SONOS NAND Flash memory array featuring arch-shaped silicon fin and extended word lines (WL) is proposed to improve virtual source/drain (VSD) performance. The arch shape concentrates electric field, resulting in higher electron concentration at the VSD region and higher on -state cell current. In addition, the extended WL process improves the short-channel-effect (SCE) immunity and I - V characteristics. To verify these, an arch VSD NAND array device was fabricated and characterized. The integrated device shows very small SCE while obtaining high on-state cell current. Program and disturbance characteristics of the device are also confirmed.
    IEEE Electron Device Letters 01/2011; · 2.79 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Negative bias-induced instability of amorphous hafnium indium zinc oxide (alpha-HIZO) thin film transistors (TFTs) was investigated at various temperatures. In order to examine temperature-induced effects, fabricated TFTs with different combinations of gate insulator and gate metal were stressed by a negative gate bias at various temperatures. As a result, it is proved that negative bias-induced hole-trapping in the gate insulators and temperature-enhanced electron injection from the gate metals occurs at the same time at all temperatures, and the instability of HIZO TFT is more affected by the dominant factor out of the two mechanisms.
    Applied Physics Letters 01/2011; 98. · 3.79 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Modern VLSI technology has been developed with continuous scaling of MOSFET. However, as MOSFET has been scaled down, a lot of critical issues have risen and resulted in a considerable degradation of individual devices [1]. On the other hand, owing to its periodic on/off characteristic, single-electron transistor (SET) attracts attention with its promising performance. But, in general, fabricating SET, silicon-on-insulator (SOI) wafers have been used for their leakage current through buried oxide (BOX) on the substrate region [2]. However, in this paper, we propose a vertical structure that is fabricated on a bare wafer, not on a SOI wafer, and the fabrication process with which small size of a quantum dot (QD) can be formed more easily than previous works [1][3]. Since the smaller QD a SET has, the better operation characteristic it has at room temperature (RT), the characteristic of the SET device can be observed more clearly than previous works with the simple process to downsize a QD.
    01/2011;
  • [Show abstract] [Hide abstract]
    ABSTRACT: Recently, 3D stacked NAND flash architectures have been proposed to solve scaling limit of the planar NAND flash memory based on floating-gate type [1]-[2]. However, theses structures have several drawbacks. For TCAT[1], declined hole-etch slope leads to different curvature radius of each stacked active layers. Consequently, different elecric field is applied to each layer in program operation, which causes the threshold voltage distribution problem. In case of VSAT[2], it is almost impossible to implement metal gate structure. Also, VSAT has the limitation of the stacking extendability due to inefficient bit line current flow (going up and down).
    Solid-State Electronics 01/2011; 78. · 1.48 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, we investigate the threshold voltage disturbance caused by programmed adjacent cells in virtual source/drain (VSD) NAND flash memory device. The fringing field induced by charge in an adjacent memory node inhibits the inversion of virtual source/drain region. So, it increases the threshold voltage of the read cell. This is a drawback for the multi-level cell (MLC) operation. The device simulation and measurement data of fabricated devices show that the disturbance increases as the cell gate length and VSD length decreases. It can be minimized by the electric field concentration induced by the arch shape structure.
    Japanese Journal of Applied Physics 01/2011; 50. · 1.07 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: As the needs for high density NAND flash memory have been dramatically increasing, the memory density has also increased by scaling down the technology node. As the scaling of NAND flash memory is accelerated, the short channel effect is more severe and further scaling down is faced with process limitations. So, various types of 3D stacked NAND flash memory has been introduced and reported for ultra-high-density data storage and Fig. 1 shows one of the previously reported 3D stacked NAND flash memory structures [1–3]. However, as the distance between layers is reduced, several channel coupling problems are emerging. In this paper, we investigate the self boosting disturbance induced by channel coupling between layers in the 3D stacked NAND flash memory.
    01/2011;
  • [Show abstract] [Hide abstract]
    ABSTRACT: Supply voltage (VDD) scaling has been an important issue as the CMOS scaling down. Scaling of devices induces large leakage current due to Short Channel Effects (SCEs). Also, Subthrehold Swing (SS) value of CMOS devices is theoretically limited to 60 mV/dec. Various structures have been proposed to overcome power dissipation problems, one of which is the TFETs [1-2]. However, TFET has two critical drawbacks such as low on-current level and ambipolar behaviors. To overcome these disadvantages, TFET using hetero-gate dielectric materials has been lately reported [3]. Although this TFET has low SS and high on-current level, it is difficult to control dielectric alignment between high-k material and SiO2 in the process. Thus, we introduce an improved TFET in terms of fabrication and performance.
    Semiconductor Device Research Symposium (ISDRS), 2011 International; 01/2011
  • [Show abstract] [Hide abstract]
    ABSTRACT: In order to overcome the limitation of a multibit silicon-oxide-nitride-oxide-silicon (SONOS) memory with multistorage nodes, we propose a unique 3-D vertical NOR (U3VNOR) array architecture. The U3VNOR has a vertical channel so that it is possible to have a long enough channel without extra cell area. Therefore, we can avoid the problems such as redistribution of injected charges, second-bit effect, and short-channel effect. Also, it is the most integrated flash architecture having the smallest unit cell size, which is 1 F<sup>2</sup>/bit. In this paper, we present the fabrication method and the operation voltage scheme of the U3VNOR. In addition, through numerical simulation, we verify its program and erase characteristics. Due to its high density and reliable multibit operation, the U3VNOR is a promising structure for the future high-density NOR flash memory.
    IEEE Transactions on Nanotechnology 02/2010; · 1.80 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, we present a detailed study of the physical dynamics of the program/erase (P/E) operations in nitride-based NAND-type charge trapping silicon-oxide-nitride-oxide-silicon (SONOS) flash memories. By calculating the internal oxide fields, tunneling currents, and trapping charges, we evaluated the simple charge trapping mechanism. We calculated transient P/E threshold voltage (VT) shift considering the ONO fields and tunneling currents. All the parameters were obtained using totally physics-based equations with no fitting parameters or optimization steps. The results show conventional NAND SONOS flash memory P/E characteristics in the Fowler-Nordheim (FN) operation regime. Also, these P/E simulation results agree with the measurement data of 30× 70 nm2 (L× W) SONOS flash memory devices that have 2.3/12/4.5 and 3/9/7 nm ONO stack layers. This model fully accounts for the VT shift as a function of the applied gate voltage, transient time, and thicknesses of silicon oxide and silicon nitride layers, which can be used for optimizing the ONO thicknesses and the parameters for improving performance.
    Japanese Journal of Applied Physics 01/2010; 49(8). · 1.07 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this study, the influence of sidewall thickness on the threshold voltage and on-current of L-shaped Impact-ionization metal-oxide-semiconductor transistor (I-MOS) is investigated. For the sidewall thickness in the range of 10 nm to 20 nm, the devices of thicker sidewall show lower on-current and higher threshold voltage. This is because the electron concentration between the channel and the most active ionization region rapidly decreases as the sidewall gets thicker. As a result, a precise control of sidewall formation is needed in fabricating L-shaped I-MOS devices. Also, obtaining the required on-current and reliability at the same time, as well as suppressing device variability due to sidewall thickness variation, is expected to be challenging.
    01/2010;
  • [Show abstract] [Hide abstract]
    ABSTRACT: Since recent mobile electronic devices have started to adopt NAND flash memory as their main data storage device, the demand for low cost and high density NAND flash memory has been rapidly increasing. As a promising candidate, nanowire SONOS NAND flash memory array has been introduced and reported for highly scalable device structure. However, since it is hard to bias floating body of memory cells, a reliable erase operation is not easy for nanowire NAND flash memory technology. So, a method which uses the hole current generated by GIDL near the select gate has been proposed for erase operation of this structure.This paper investigates a new method for significantly enhancing the erase speed of nanowire SONOS NAND flash memory through the use of silicide drain. Compared with the array which has the conventional n-doped drain, the proposed array structure has much faster erase speed because of the lower and narrower barrier. And, on-state cell current degradation caused by Schottky barrier can be negligible on condition that drain bias is over 1V. This result can be useful in gate-all-around type NAND flash memory design.
    01/2009;
  • [Show abstract] [Hide abstract]
    ABSTRACT: A NAND flash memory array having extended word-lines is proposed. Without scarifying areal density, both physical gate length and charge storage node size are increased through the word-line extension process. Simple fabrication flow is delivered and device performances in a viewpoint of the short channel effect are simulated. The effect of gate length variation on the cell threshold voltage (VTH) distribution is addressed. Programming characteristics in the inversion-type source/drain NAND flash memory are also described. Some side effects concerned with the program disturbance and cell-to-cell interference are investigated in comparison with the conventional NAND flash memory.
    Japanese Journal of Applied Physics 01/2009; 48. · 1.07 Impact Factor