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ABSTRACT: A compact (0.01mm<sup>2</sup>) coarse-fine time-to-digital converter (TDC) in 40nm LP CMOS achieves 5.5ps resolution using parallel delay lines. A 6fJ/conversion step efficiency is achieved thanks to efficient residue calculation. A 0.8LSB single-shot precision and low DNL are reached thanks to simple calibration which is possible in fractional-N PLLs. Further, metastability avoidance and digital error correction are implemented. This 14-bit architecture operates at a 40MS/s reference clock.
Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE; 06/2010
