U. Madawala

University of Auckland, Auckland, Auckland, New Zealand

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Publications (7)6.27 Total impact

  • Article: Techniques for Conditioning Bit-Stream Signals for Single-Phase Power Electronics Applications
    J.B.B. Bradshaw, U. Madawala, N. Patel
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    ABSTRACT: Bitstream-based control, which uses one-bit-wide signals to control power electronics applications, is a new approach for controller design. Bit-Stream signals can be directly applied to control electronic devices, but the high-frequency nature of bitstream signals can lead to excessive switching losses. Thus, it is essential to downsample bitstream signals to reduce switching losses to acceptable levels. This paper presents a novel modulator, which downsamples high-frequency bitstreams to low-frequency switching signals that are suitable for driving two-level half-bridge or three-level full-bridge inverters. Methods for compensating for switch dead time and balancing switching losses of the inverter legs are presented, and the performance of the proposed modulators are compared to the standard pulse width modulation strategies. Simulation and experimental results of a 2-kW single-phase inverter show that the proposed bitstream modulators consume fewer logic resources, produce spread-spectrum output currents, and can deliver lower total harmonic distortion than similar fixed-frequency pulse width modulators.
    IEEE Transactions on Power Electronics 04/2012; · 4.65 Impact Factor
  • Article: Bit-stream implementation of a phase-locked loop
    J. Bradshaw, U. Madawala, N. Patel
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    ABSTRACT: Bit-stream is a new technique for controlling power electronics applications by interconnecting appropriate control elements inside an field programmable gate array (FPGA). This paper presents a bit-stream-based phase locked loop (PLL), which is essential for the implementation of sophisticated power electronics control systems using bit-streams. The proposed PLL consists of a phase detector, loop filter and numerically controlled oscillator, each of which is designed using standard analogue methods and converted to equivalent bit-stream elements. The bit-stream-based PLL is modelled using Matlab/Simulink and ModelSim, and results show that the PLL successfully locks onto a 50 Hz three-phase voltage source. Experimental results of a prototype, constructed using an Altera Cyclone II FPGA and controlled using a bit-stream-based PLL, are presented and compared to a similar, microprocessor-based, PLL to demonstrate that the bit-stream-based PLL successfully locks onto the line voltage waveform. The practical viability of the proposed bit-stream PLL is investigated using a prototype three-phase, 3 kW, controlled rectifier. The experimental implementation of the PLL requires approximately 350 logic elements.
    IET Power Electronics 02/2011; · 1.62 Impact Factor
  • Conference Proceeding: Techniques for conditioning high-speed bit-stream signals for power electronic applications
    J. Bradshaw, U. Madawala, N. Patel
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    ABSTRACT: The bit-stream technique, which uses one bit wide and low to high frequency digital signals to represent control values, is a new approach for designing controllers. A bit-stream signal can directly be used to control power electronics systems but its inherently high switching speeds may lead to excessive switching losses, which are a major concern for many potential power electronic applications. This paper therefore proposes three different conditioning techniques or modulators, which convert high speed bit-stream signals into relatively low speed bit-stream signals that are suitable for bit-stream control of power electronics systems. The performance of the proposed modulation techniques, namely standard fixed-frequency PWM, standard down-sampled bit-streams (SDBS) and hysteretically down-sampled bit-streams (HDBS), is investigated in detail, using low speed bit-stream signals generated by the modulators as gate drive signals for a single phase DC to AC inverter. Simulation results show that the HDBS approach offers spread spectrum operation, lower switching losses than PWM, and uses the fewest hardware resources. Experimental results confirm that the HDBS modulator operates as expected, and produces an output current with a lower THD than a conventional PWM design.
    Industrial Electronics, 2009. IECON '09. 35th Annual Conference of IEEE; 12/2009
  • Conference Proceeding: Bit-Stream control of three phase reversible rectifiers
    J. Bradshaw, U. Madawala, N. Patel
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    ABSTRACT: Bit-stream is a new technique for controlling power electronics applications by interconnecting appropriate control elements inside an FPGA. This paper presents a Bit-Stream based controller for a three phase, 400 V / 7 kVA reversible rectifier, which is used to transfer power between an AC line and a DC bus in a controlled manner. The proposed controller is based on vector control techniques, which provide independent control of the real and reactive power flow through the rectifier, and is the first Bit-stream based vector controller to be reported in literature. The controller is implemented by interconnecting Bit-Stream controller blocks, which implement Clarke and Park's Transformations, phase locked loops, current controllers and space vector modulation. Simulations using Matlab / Simulink and ModelSim show that the controller successfully manages the power flow through the rectifier, and is not disturbed by sudden changes in the AC line voltage. The inherently parallel nature of Bit-Stream control systems ensures that the addition of extra functionality to the controller will not affect system performance, whereas microprocessor based systems may reach execution time limits as control complexity increases.
    Energy Conversion Congress and Exposition, 2009. ECCE 2009. IEEE; 10/2009
  • Conference Proceeding: Implementation of Phase Locked Loops using Bit-Stream control techniques
    J. Bradshaw, N. Patel, U. Madawala
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    ABSTRACT: Some utility-connected power electronics applications such as reversible rectifiers and active power filters need accurate measurements of the utility phase angle. A phase locked loop (PLL) is an important component of such systems. This paper describes the development of a three phase PLL for utility angle measurement using a new bit-stream control technique, which has several advantages when used for power electronics applications. The PLL structure is developed from standard design equations, and then modeled in full detail using VHDL descriptions of Bit-Stream components. Comparisons of VHDL simulation results with Matlab / Simulink models of the PLL shows that the Bit-Stream version behaves as expected, demonstrating that the Bit-Stream technique is suitable for the implementation of PLL systems.
    Industrial Technology, 2009. ICIT 2009. IEEE International Conference on; 03/2009
  • Conference Proceeding: Brushless DC motor control using bit-streams
    N. Patel, U. Madawala
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    ABSTRACT: The control of a brushless dc (BLDC) motor, using bit-streams is presented. Bi-polar signals are represented using a uniformly weighted bit-stream which can be manipulated using simple digital logic to create a variety of control actions. This paper presents the functional elements required for the implementation of a proportional integral (PI) controller to affect speed and torque control on a BLDC motor. Preliminary experimental results on a standard BLDC motor using an Altera field programmable gate array (FPGA) are presented and show the viability of this technique.
    Control, Automation, Robotics and Vision, 2008. ICARCV 2008. 10th International Conference on; 01/2009
  • Conference Proceeding: A bit-stream based scalar control of an induction motor
    N. Patel, U. Madawala
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    ABSTRACT: A field programmable gate array (FPGA) implementation of constant V/f scalar controller is presented. The implementation technique uses uniformly weighted single-bit streams. Various building blocks which are required for the implementation have been detailed. Preliminary experimental results on a three phase induction motor (IM) show that the technique is a viable alternative to standard techniques. The implementation uses approximately 600 logic elements (LE) on an Altera Stratix FPGA. Also this method is inherently parallel in nature and hence timing difficulties, as a result of an increase in complexity, are minimized.
    Industrial Electronics, 2008. IECON 2008. 34th Annual Conference of IEEE; 12/2008

Institutions

  • 2008–2012
    • University of Auckland
      • Department of Electrical & Computer Engineering
      Auckland, Auckland, New Zealand