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ABSTRACT: Switch fabrics for 100 Gigabit Ethernet systems pose high demands in terms of delay and scalability. In this paper we analyze the performance of a Clos-based switch fabric under uniform and bursty traffic, and compare its performance to a crossbar-based switch design for benchmarking. In particular, we focus on a Clos-design using a Space-Memory-Memory (SMM) configuration, which has recently gained increased interest due to its reduced hardware complexity. The traffic between the input and the central modules is distributed in either a static, random or Desynchronized Static Round Robin (DSRR) fashion. Simulation results show that for uniform Bernoulli traffic, the DSRR scheme outperforms the others. Under bursty traffic, the DSRR scheme and the random scheme achieve similar performance. The static scheme performs the worst for both cases. Comparing the SMM design to an Output Queued crossbar switch only reveals a minor performance penalty, which can be compensated by the high scalability, robustness and low complexity of the Clos-based design for high speed switching systems.
Optical Network Design and Modeling (ONDM), 2011 15th International Conference on; 03/2011
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ABSTRACT: The Internet users behavioural patterns are migrating towards bandwidth-intensive applications, which require a corresponding capacity extension. The emerging 100 Gigabit Ethernet (GE) technology is a promising candidate for providing a ten-fold increase of todays available Internet transmission rate. As the need for 100 Gigabit Ethernet equipment rises, so does the need for equipment, which can properly test these systems during development, deployment and use. This paper presents early results from a work-in-progress academia-industry collaboration project and elaborates on the challenges of performing bit error rate testing at 100Gbps. In particular, we show how Bit Error Rate Testing (BERT) can be performed over an aggregated 100G Attachment Unit Interface (CAUI) by encapsulating the test data in Ethernet frames at line speed. Our results show that framed bit error rate testing can be performed at speeds exceeding 100Gbps using commercially available Field Programmable Gate Arrays (FPGAs). Even though extensive parallelization is used to achieve this goal, the resulting resource consumption of the proposed design remains relatively modest, leaving plenty of room for additional functionality besides the bit error rate tester.
High Performance Switching and Routing (HPSR), 2010 International Conference on; 07/2010
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ABSTRACT: Ethernet as a transport technology has, up to now, lacked the features such as network layer architecture, customer separation and manageability that carriers require for wide-scale deployment. However, with the advent of PBB-TE and T-MPLS, it is now possible to use Ethernet as a transport technology, making the use of Ethernet as a convergence layer for Next Generation Networks a distinct possibility. Triple Play services, in particular IPTV, are expected to be a main drivers for carrier Ethernet, however, a number of challenges must be addressed including QoS enabled control plane, enhanced OAM functions, survivability and the increased bandwidth requirements of carrier class systems. This article provides an overview of PBB-TE and T-MPLS and demonstrates how IPTV services can be realized in the framework of Carrier Ethernet. In addition we provide a case study on performing bit error rate (BER) measurements on the aggregated 100G stream.
WSEAS Transactions on Communications 9(3):153-164.
