R.W. Brodersen

University of California, Berkeley, Berkeley, California, United States

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Publications (309)229.79 Total impact

  • Dejan Marković · Robert W. Brodersen · Rashmi Nanda
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    ABSTRACT: This chapter discusses DSP techniques used to design digitally intensive front ends for radio systems. Conventional radio architectures use analog components and RF filters that do not scale well with technology, and have poor tunability required for supporting multiple modes of operation. Digital CMOS scales well in power, area, and speed with each new generation, and can be easily programmed to support multiple modes of operation.
    DSP Architecture Design Essentials, 01/2012: pages 255-276; , ISBN: 978-1-4419-9659-6
  • Dejan Marković · Robert W. Brodersen · Rashmi Nanda · Borivoje Nikolić
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    ABSTRACT: This chapter introduces the fundamentals of digital filter design, with emphasis on their usage in radio applications. Radios by definition are expected to transmit and receive signals at certain frequencies, while also ensuring that the transmission does not exceed a specified bandwidth. We will, therefore, discuss the usage of digital filters in radios, and then study specific implementations of these filters, along with pros and cons of the available architectures.
    DSP Architecture Design Essentials, 01/2012: pages 111-143; , ISBN: 978-1-4419-9659-6
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    Anantha Chandrakasan · Samuel Sheng · R. W. Brodersen
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    ABSTRACT: Recently, the concept of “personal communications” has come to the forefront of communications research, in which individual users will have portable, private access to fixed computing facilities. The ultimate goal is to provide a personal communications system (PCS), which will move information of all kinds to and from people in all locations, through an advanced wireless network supporting a wide range of services. As a step beyond today’s portable computers, a high-speed wireless link allows the advent of small, lightweight, multimedia graphics terminals, whose primary function would be to connect the user instantaneously and transparently into powerful fixed processing units and data storage. It would be capable of providing speech communication, data transfer and retrieval, computing services, and high-quality, full-motion video. Since traditional keyboard or mouse interfacing is unwieldy in a portable unit, control will be provided through speech recognition. Of course, the success of the network concept hinges upon the capability of the system to provide sufficiently high data rates. Even with the best compression schemes known today, fullmotion, high-resolution digital video alone requires data rates upwards of 1Mbit/sec[12]; the terminals and network must be designed to achieve this throughput (figure 1), taking advantage of the 1+ GBit/sec capabilities of the fixed fiber-optic backbone.
    Third Generation Wireless Information Networks, 06/2011: pages 75-97;
  • Cheng C. Wang · Changchun Shi · Robert W. Brodersen · Dejan Marković
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    ABSTRACT: This paper presents an automated tool for floating-point to fixed-point conversion. The tool is based on previous work that was built in MATLAB/Simulink environment and Xilinx System Generator support. The tool is now extended to include Synplify DSP blocksets in a seamless way from the users' view point. In addition to FPGA area estimation, the tool now also includes ASIC area estimation for end-users who choose the ASIC flow. The tool minimizes hardware cost subject to mean-squared quantization error (MSE) constraints. To obtain more accurate ASIC area estimations with synthesized results, 3 performance levels are available to choose from, suitable for high-performance, typical, or low-power applications. The use of the tool is first illustrated on an FIR filter to achieve over 50% area savings for MSE specification of 10−6 as compared to all 16-bit realization. More complex optimization results for chip-level designs are also demonstrated.
    05/2011; 2011(11). DOI:10.5402/2011/414293
  • Jing Yang · Thura Lin Naing · Robert W. Brodersen
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    ABSTRACT: An asynchronous 6 bit 1 GS/s ADC is achieved by time interleaving two ADCs based on the binary successive approximation (SA) algorithm using a series capacitive ladder. The semi-closed loop asynchronous technique eliminates the high internal clocks and significantly speeds up the SA algorithm. A key feature to reduce the power in this design involves relaxing the comparator requirements using an error correction technique, which can be viewed as an extension of the SA algorithm to remove degradation due to metastability. Fabricated in 65 nm CMOS with an active area of 0.11 mm<sup>2</sup>, it achieves a peak SNDR of 31.5 dB at 1GS/s sampling rate and has a total power consumption of 6.7 mW.
    IEEE Journal of Solid-State Circuits 09/2010; 45(8-45):1469 - 1478. DOI:10.1109/JSSC.2010.2048139 · 3.01 Impact Factor
  • Jing Yang · Thura Lin Naing · Robert W. Brodersen
  • David Amory Sobel · R.W. Brodersen
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    ABSTRACT: A low-power mixed-signal baseband analog front-end for 60 GHz, 1 Gb/s wireless communications has been implemented in a standard 90 nm CMOS process. The receiver is capable of operating under indoor multipath scenarios, resolving channels with up to 32 ns multipath delay spread. It uses mixed-signal equalization and carrier recovery in order to minimize the dynamic range requirements of the analog-to-digital converter circuitry. A new mixed-signal carrier phase recovery architecture, utilizing a replica tuning scheme employing Gilbert quad variable-gain amplifiers is introduced. The analog-to-digital converters use an active averaging technique that decouples the preamplifier gain from the averager input range, enabling enhanced suppression of mismatch-induced nonlinearities. These techniques enable a front-end with 6-bit linearity and dynamic range, while dissipating a low power consumption of 55 mW.
    IEEE Journal of Solid-State Circuits 05/2009; 44(4)(4-44):1281 - 1289. DOI:10.1109/JSSC.2009.2014731 · 3.01 Impact Factor
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    ABSTRACT: A 100 MS/s pipelined ADC is digitally calibrated by a slow SigmaDelta ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411 kHz sinusoidal input, the peak SNDR improves from 28 dB to 59 dB and the SFDR improves from 29 dB to 68 dB. The complete 0.13 mu ADC SoC occupies a die size of 3.7 mm times 4.7 mm, and consumes a total power of 448 mW.
    Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE; 10/2008
  • Source
    H.K.-H. So · R. Brodersen
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    ABSTRACT: This paper presents the design and implementation of BORPHpsilas kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics resembling that of conventional UNIX file I/Os, an FPGA accesses the file system through a special hardware system call interface. By extending the semantics of a UNIX pipe, a single file system access mechanism is used for both regular file I/O, as well as for hardware/software and hardware/hardware data streaming. An FPGA design may switch between different communication modes dynamically during run time by means of file redirection. Design trade-offs among system manageability, user usability and application performance are explored. An example of constructing a video processing system during run time using commodity software and FPGA applications connected by pipes is used to demonstrate the feasibility and potential of such FPGA-centric file system access capability.
    Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on; 10/2008
  • Kevin Camera · R.W. Brodersen
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    ABSTRACT: Large-scale, direct-mapped FPGA computing systems are traditionally very difficult to debug due to the high level of parallelism and limited access to internal signal values. In our approach to mitigate this problem, the concepts of variables and process control are brought into the FPGA hardware domain. Declarations made in the design environment are translated into logic inserted automatically into the hardware implementation. Variables provide full read/write access to hardware signals during runtime, complete with same-cycle, dynamically definable assertion checking. System data is cached via attached DRAM, providing deep variable history and the ability to ldquorewindrdquo system state. Process execution can also be controlled by the user manually or through the declaration of breakpoints. All debugging controls are available via a remote graphical user interface, which also supports back-annotation in the input design for improved data visibility and comprehension. Empirical examples have shown the logic overhead for the above functionality to be approximately 66 slices per 16-bit variable with full assertion checking on a Virtex-II Pro device, plus the fixed requirements of the debug controller and memory interface.
    Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on; 10/2008
  • David A. Sobel · R.W. Brodersen
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    ABSTRACT: A low-power, mixed-signal, baseband analog front end for 60 GHz 1 Gb/s wireless communications has been implemented in a standard 90 nm CMOS process. The receiver is capable of operating under indoor multipath scenarios, resolving channels with up to 32 ns multipath delay spread. It uses mixed-signal equalization and carrier recovery in order to minimize the dynamic range requirements of the converter circuitry, resulting in a low power consumption of 55 mW.
    VLSI Circuits, 2008 IEEE Symposium on; 07/2008
  • Source
    Hayden Kwok-Hay So · Robert Brodersen
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    ABSTRACT: This paper presents the design of BORPH's file system layer for FPGA-based reconfigurable computers. BORPH provides user FPGA designs that execute as hardware processes access to the general file system using familiar UNIX file I/O semantics. Such capability provides FPGA designers an intuitive interface not only for regular file I/O, but also for representing streaming hardware/software and hardware/hardware communication using UNIX pipes. Design trade-offs among system manageability, user usability and application performance are explored. A case of mixed hardware/software video processing is presented as a proof-of-concept.
    Field-Programmable Custom Computing Machines, 2008. FCCM '08. 16th International Symposium on; 05/2008
  • Source
    Hayden Kwok-Hay So · Robert W. Brodersen
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    ABSTRACT: This paper explores the design and implementation of BORPH, an operating system designed for FPGA-based reconfigurable computers. Hardware designs execute as normal UNIX processes under BORPH, having access to standard OS services, such as file system support. Hardware and software components of user designs may, therefore, run as communicating processes within BORPH's runtime environment. The familiar language independent UNIX kernel interface facilitates easy design reuse and rapid application development. To develop hardware designs, a Simulink-based design flow that integrates with BORPH is employed. Performances of BORPH on two on-chip systems implemented on a BEE2 platform are compared.
    ACM Transactions on Embedded Computing Systems 02/2008; 7(2). DOI:10.1145/1331331.1331338 · 0.47 Impact Factor
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    Conference Paper: Radio Testbeds Using BEE2
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    ABSTRACT: Flexible radio testbeds are being designed using the Berkeley Emulation Engine (BEE2) platform. Narrow-band and wide-band platforms are discussed which can accommodate a full spectrum of wireless multiple radios for wide and narrowband applications. The BEE2 programming and debugging capabilities, using Simulink and Linux augmented with the BORPH operating system, provide a high level design environment. Applications are discussed which portray the flexibility of these testbeds and the ability to demonstrate realistic scenarios, as well as comprehensively evaluate and verify theoretical results.
    Signals, Systems and Computers, 2007. ACSSC 2007. Conference Record of the Forty-First Asilomar Conference on; 12/2007
  • Source
    S.-W.M. Chen · Robert W. Brodersen
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    ABSTRACT: An impulse radio architecture utilizing a simple analog front end along with digital complex signal processing is proposed to allow a low complexity implementation of a 3.1-10.6 GHz ultrawideband (UWB) radio. The proposed system transmits passband pulses using a pulser and antenna, and the receiver front-end downconverts the signal frequency via subsampling, thus, requiring substantially less hardware than the existing direct conversion approach. After the analog-to-digital converter (ADC), the signal is projected into complex signal domain to perform matched filtering to not only mitigate the timing sensitivity induced by analog circuit impairment, but also extract the fine time resolution provided by the wideband nature of a UWB signal. The performance and potential usages of these complex signal processing blocks are solved and compared with different complex signal transformations. Based on the proposed architecture, the system specifications and implementation issues are further analyzed and emulated by system-level simulations with measured signal and noise. The subsampling ADC is considered as the most challenging circuit block and has recently been proven with a low-power low-cost fully integrated CMOS solution. Finally, a radio prototype built with discrete components is used for proof of concept.
    IEEE Transactions on Signal Processing 11/2007; 55(10-55):5018 - 5031. DOI:10.1109/TSP.2007.896056 · 2.79 Impact Factor
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    S.M. Mishra · R.W. Brodersen
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    ABSTRACT: Cognitive radio technology enables the opportunistic operation of secondary devices in frequency bands allocated to primary users. In this paper we explore how this technology can enable ultra-wideband (UWB) systems to coexist with primary users. The distinguishing aspect of cognitive radio technology is the ability to detect and avoid primary users. We discuss two options for detecting the presence of primary devices - energy detection and preamble detection. The presence of multiple UWB devices can aid detection by enabling cooperative sensing of the primary. We analyze various techniques for cooperative sensing which differ in the amount of information they need to exchange between radios and the regime in which they are potentially advantageous. Furthermore, the wideband aspect of UWB offers many challenges to detection but also facilitates the detection process in several ways. These distinguishing aspects of wideband detection are also highlighted in this paper.
    Ultra-Wideband, 2007. ICUWB 2007. IEEE International Conference on; 10/2007
  • Source
    D. Markovic · Chen Chang · B. Richards · H. So · B. Nikolic · R.W. Brodersen
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    ABSTRACT: A unified algorithm-architecture-circuit co-design environment for dedicated signal processing hardware is presented. The approach is based on a single design description in the graphical Matlab/Simulink environment that is used for FPGA emulation, ASIC design, verification and chip testing. This unified description enables system designer with a visibility through several layers of design hierarchy down to circuit level to select the optimal architecture. The tool flow propagates up circuit-level performance and power estimates to rapidly evaluate architecture-level tradeoffs. The common Simulink design description minimizes errors in translation of the design between different descriptions, and eases the verification burden. The FPGA used for emulation can be used as a low-cost tool for testing of the fabricated ASIC. The approach is demonstrated on an ASIC for 4times4 MIMO signal processing.
    Custom Integrated Circuits Conference, 2007. CICC '07. IEEE; 10/2007
  • Source
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    ABSTRACT: Ultra-wideband (UWB) impulse radio is a promising technique for low-power bio-medical communication systems. While a range of analog and digital UWB architectures exist, the mostly-digital approach without analog down-conversion enables better technology scaling and signal processing flexibility. Furthermore, recently proposed sub-sampling schemes and advances in high-speed ADC circuit design are helping to make this approach more feasible at low power. However, architectures that directly sample the received signal are more vulnerable to sampling jitter. Currently, there does not exist a model describing the impact of sampling jitter making it difficult to determine appropriate tolerances or to establish the feasibility of digital architectures. To address this problem, we have developed a model of sampling jitter and derived a generic bit error rate expressions for a digital UWB modem with sampling jitter, additive noise, and imperfect channel estimation in a generic multipath environment. We then use this model to investigate the performance of sub-sampled digital UWB in a body area network. This paper explains this analytical model and compares it with simulations results for communication around the body.
    Communications, 2007. ICC '07. IEEE International Conference on; 07/2007
  • Source
    Jing Yang · R.W. Brodersen · David Tse
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    ABSTRACT: The discrepancy between perceived spectrum shortage from the FCC allocation map and the actual abundance of available spectrum is a motivation for Cognitive Radios, which locate and transmit in the unused or lightly used bands. If a digital approach is taken to provide the necessary radio flexibility to exploit this sparsity, there is a challenging dynamic range requirement in the analog to digital conversion, since there are large interfering signals which are effectively in-band and can not be removed by fixed RF pre-filtering. Using a mixed analog digital system architecture which uses multiple low accuracy ADCs with digital adaptive filters, it is possible to increase the effective dynamic range of the input by subtracting off the unwanted signals in the time domain.
    Communications, 2007. ICC '07. IEEE International Conference on; 07/2007
  • Source
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    ABSTRACT: Cognitive radios have been advanced as a technology for the opportunistic use of underutilized spectrum wherein secondary devices sense the presence of the primary user and use the spectrum only if it is deemed empty. Spectral cognition of this form can also be used by regulators to facilitate the dynamic coexistence of different service types. An example of this is the operation of ultra-wideband devices in WiMAX bands: UWB devices must detect and avoid WiMAX devices in certain regulatory domains. In this article we start by discussing various options for detection and avoidance. We then describe the obstacles faced in achieving robust detection and avoidance with an on-chip implementation of basic DAA functionality. Finally, we present measurement results for operation of a single UWB device with a WiMAX system. This interaction also highlights the problem of dealing with listen before speak primaries where secondary transmission could interfere by blocking the primary's access to the medium.
    IEEE Communications Magazine 07/2007; 45(6-45):68 - 75. DOI:10.1109/MCOM.2007.374435 · 4.01 Impact Factor

Publication Stats

16k Citations
229.79 Total Impact Points


  • 1976–2012
    • University of California, Berkeley
      • • Department of Electrical Engineering and Computer Sciences
      • • Berkeley Wireless Research Center
      • • Computer Science Division
      Berkeley, California, United States
  • 2006–2007
    • University of California, Los Angeles
      • Department of Electrical Engineering
      Los Angeles, CA, United States
  • 1991–2002
    • Stanford University
      • Department of Electrical Engineering
      Palo Alto, California, United States
    • National Chiao Tung University
      • Department of Electronics Engineering
      Hsinchu, Taiwan, Taiwan
  • 1995–1998
    • AT&T Labs
      Austin, Texas, United States
    • Massachusetts Institute of Technology
      Cambridge, Massachusetts, United States
  • 1986
    • imec Belgium
      Louvain, Flemish, Belgium
  • 1984
    • University of Berkley
      Berkley, Michigan, United States
  • 1974–1975
    • Texas Instruments Inc.
      Dallas, Texas, United States