ABSTRACT: The scope of the European project TIPS (Thin Interconnected Package Stacks) is the fabrication of ultra thin packages for electronic components and the subsequent stacking and interconnection of those packages to form highly compact modules. In the first part of this paper approaches to fabricate ultra thin 10 × 10 mm packages by embedding technologies for chips into printed circuit board environments will be discussed. One technology uses commercial flexible printed circuit board substrates (polyimide sandwiched in Cu layers) and respective fabrication processes. After initial patterning of the Cu the chips are die bonded to the flex substrates and subsequently laminated into build up layers. Electrical contact between the chip and a fan out routing on the outer layer of the package are made by micro via formation, electroplating and wet chemical structuring of the metal layers. The thickness of the embedded components is constricted to 50 μm in order to constrain the package thicknesses to a maximum of 100 μm with this approach. The alternative approach, the ultra thin chip package (UTCP) technology, aims at package thicknesses around 60 μm. In this case 20 μm thick chips are die-bonded to thin polyimide layer. A photo-definable polyimide is then applied over the assembled chips by spin-on technique. Contact pads are opened by exposure and development of the polyimide, followed by metal sputtering, electroplating and etching. In this approach the thickness of embedded components is typically 20-30 μm and final package thickness is in the range of 60 μm. In both approaches the packages are fabricated as batches consisting of 150 × 150 mm sheets of flex substrates. Stacking of individual packages can be performed in an automated package by package placement process using a frame as alignment tool and typical flexible printed circuit boards adhesives. In this way only known-good-packages are stacked in o-
rder to minimize yield loss. However, a more straight forward process is stacking of the packages using fabrication batches and established multilayer printed circuit board technologies. The disadvantage is the potential yield loss if one of the packages in a stacked layer is faulty. For either type of stacking process the individual stacks have to be milled out of the stack fabrication batch. Development issues, design considerations and results of first fabrication runs will be presented and discussed.
Electronic System-Integration Technology Conference (ESTC), 2010 3rd; 10/2010