Publications (2)3.23 Total impact
-
Article: BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel
[show abstract] [hide abstract]
ABSTRACT: A 1-Gbit DRAM with 5.8-Gb/s/pin unidirectional differential I/Os was implemented by 70 nm DRAM process and a main memory module with dual in-line memory module was assembled. The implemented DRAM chips have control methods for core noise injection and a cyclic redundancy check (CRC) generator for outer-data inner-command architecture. Measurements for bit error rate and jitter performance of the transmitter was performed on an electrical test board which emulates the real memory system's environment. Also, the effect on power noise was analyzed from the DRAM chips with three class values of power decoupling capacitance for the peripheral part. The results show that no additional coding for the differential I/O protection in DRAM, like CRC, is required up to 5.8-Gb/s/pin operation.IEEE Journal of Solid-State Circuits 12/2009; · 3.23 Impact Factor -
Conference Proceeding: Self-calibrating transceiver for source synchronous clocking system with on-chip TDR and swing level control scheme
[show abstract] [hide abstract]
ABSTRACT: A transceiver chip with per-pin de-skew and read latency detection scheme utilizing on-chip TDR was implemented in 60nm DRAM process for the interface with source synchronous clock system. Without multi-phase clock, each time skew between Strobe and 16 Data was corrected within 0.028UI at 1.6-Gb/s data rate. Also, the jitter reduction of 50% was measured with swing-level controlled voltage-mode driver in the absence of destination termination at 1.6-Gb/s.VLSI Circuits, 2009 Symposium on; 07/2009
Top co-authors
Top Journals
Institutions
-
2009
-
Kumoh National Institute of Technology
Seoul, Seoul, South Korea
-
