Young-Chan Jang

Kumoh National Institute of Technology, Sŏul, Seoul, South Korea

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Publications (24)7.68 Total impact

  • Pil-Ho Lee, Hyun Bae Lee, Young-Chan Jang
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    ABSTRACT: A 125 MHz 64-phase delay-locked loop (DLL) is implemented for time recovery in a digital wire-line system. The architecture of the proposed DLL comprises a coarse-locking circuit added to a conventional DLL circuit, which consists of a delay line including a bias circuit, phase detector, charge pump, and loop filter. The proposed coarse-locking circuit reduces the locking time of the DLL and prevents harmonic locking, regardless of the duty cycle of the clock. In order to verify the performance of the proposed coarse-locking circuit, a 64-phase DLL with an operating frequency range of 40 to 200 MHz is fabricated using a 0.18-mu m 1-poly 6-metal CMOS process with a 1.8 V supply. The measured rms and peak-to-peak jitter of the output clock are 3.07 ps and 21.1 ps, respectively. The DNL and INL of the 64-phase output clock are measured to be -0.338/+0.164 LSB and -0.464/+0.171 LSB, respectively, at an operating frequency of 125 MHz. The area and power consumption of the implemented DLL are 0.3 mm(2) and 12.7 mW, respectively.
    IEICE Transactions on Electronics 05/2014; E97.C(5):463-467. DOI:10.1587/transele.E97.C.463 · 0.39 Impact Factor
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    Pil-Ho Lee, Young-Chan Jang
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    ABSTRACT: This paper proposes a charge-pump phase-locked loop (PLL) with 51-phase output clock of a 125 MHz target frequency. The proposed PLL uses three voltage controlled oscillators (VCOs) to generate 51-phase clock and increase of maximum operating frequency. The 17 delay-cells consists of each VCO, and a resistor averaging scheme which reduces the phase mismatch among 51-phase clock combines three VCOs. The proposed PLL uses a 65 nm 1-poly 9-metal CMOS process with 1.0 V supply. The simulated peak-to-peak 지터 of output clock is 0.82 ps at an operating frequency of 125 MHz. The differential non-linearity (DNL) and integral non-linearity (INL) of the 51-phase output clock are -0.013/+0.012 LSB and -0.033/+0.041 LSB, respectively. The operating frequency range is 15 to 210 MHz. The area and power consumption of the implemented PLL are and 3.48 mW, respectively.
    02/2014; 18(2). DOI:10.6109/jkiice.2014.18.2.408
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    Yeon-Ho Jeong, Young-Chan Jang
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    ABSTRACT: This paper presents a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) which consists of a digital-to-analog converter (DAC), a SAR logic, and a comparator. The designed asynchronous SAR ADC with a rail-to-rail input range uses a binary weighted DAC using metal-oxide-metal (MOM) capacitor to improve sampling rate. The proposed 10-bit 10-MS/s asynchronous SAR ADC is fabricated using a 0.18- CMOS process and its active area is . The power consumption is 0.37 mW when the voltage of supply is 1.1 V. The measured SNDR are 54.19 dB and 51.59 dB at the analog input frequency of 101.12 kHz and 5.12 MHz, respectively.
    01/2014; 18(1). DOI:10.6109/jkiice.2014.18.1.129
  • Mungyu Kim, Hoon-Ju Chung, Young-Chan Jang
    IEICE Transactions on Electronics 01/2014; E97.C(6):519-525. DOI:10.1587/transele.E97.C.519 · 0.39 Impact Factor
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    Seung-Yong Lee, Pil-Ho Lee, Young-Chan Jang
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    ABSTRACT: Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.
    10/2013; 17(10). DOI:10.6109/jkiice.2013.17.10.2409
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    Han-Yeol Lee, Yu-Jeong Hwang, Young-Chan Jang
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    ABSTRACT: An active-RC channel selection filter (CSF) with the bandwidth of 40MHz and the improved linearity is proposed in this paper. The proposed CSF is the fifth butterworth filter which consists of a first order low pass filter, two second order low pass filters of a biquad architecture, and DC feedback circuit for cancellation of DC offset. To improve the linearity of the CSF, a body node of a MOSFET for a switch is connected to its source node. The bandwidth of the designed CSF is selected to be 10MHz, 20MHz and 40MHz and its voltage gain is controlled by 6 dB from 0 dB to 24 dB. The proposed CSF is designed by using 40nm 1-poly 8-metal CMOS process with a 1.2V. When the designed CSF operates at the bandwidth of 40 MHz and voltage gain of 0 dB, the simulation results of OIP3, in-band ripple, and IRN are 31.33dBm, 1.046dB, and 39.81nV/sqrt(Hz), respectively. The power consumption and layout area are and 6.71mW.
    10/2013; 17(10). DOI:10.6109/jkiice.2013.17.10.2395
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    Yeon-Ho Jeong, Young-Chan Jang
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    ABSTRACT: This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of is fabricated using a 0.18- CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.
    02/2013; 17(2). DOI:10.6109/jkiice.2013.17.2.414
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    Mungyu Kim, Young-Chan Jang
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    ABSTRACT: In this paper, a CMOS temperature sensor is proposed to measure the internal temperature of a chip. The temperature sensor consists of a proportional-to-absolute-temperature (PTAT) circuit for a temperature sensing part and a 4-bit analog-to-digital converter (ADC) for a digital interface. The PTAT circuit with the compact area is designed by using a vertical PNP architecture in the CMOS process. To reduce sensitivity of temperature variation in the digital interface circuit of the proposed temperature sensor, a 4-bit successive approximation (SA) ADC using the minimum analog circuits is used. It uses a capacitor-based digital-to-analog converter and a time-domain comparator to minimize power consumption. The proposed temperature sensor was fabricated by using a 1-poly 6-metal CMOS process with a 2.5V supply, and its operating temperature range is from 50 to . The area and power consumption of the fabricated temperature sensor are and , respectively.
    02/2013; 17(2). DOI:10.6109/jkiice.2013.17.2.378
  • Ji-Hun Eo, Yeon-Ho Jeong, Young-Chan Jang
    IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences 01/2013; E96.A(2):453-458. DOI:10.1587/transfun.E96.A.453 · 0.23 Impact Factor
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    ABSTRACT: A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are and 193.02mW.
    09/2012; 16(9). DOI:10.6109/jkiice.2012.16.9.1847
  • Ji-Hun Eo, Sang-Hun Kim, Young-Chan Jang
    06/2012; 16(6):1250-1259. DOI:10.6109/jkiice.2012.16.6.1250
  • Hyun Bae Lee, Young-Chan Jang
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    ABSTRACT: Mirrored serpentine microstrip lines are proposed for a parallel high speed digital signaling to reduce the peak far-end crosstalk (FEXT) voltage. Mirrored serpentine microstrip lines consist of two serpentine microstrip lines, each one equal to a conventional normal serpentine microstrip line. However, one serpentine microstrip line of the mirrored serpentine microstrip lines is flipped in the length direction, and thus, two serpentine microstrip lines face each other. Time domain reflectometry measurements show that the peak FEXT voltage of the mirrored serpentine microstrip lines is reduced by 56.4% of that of conventional microstrip lines and 30.0% of that of conventional normal serpentine microstrip lines.
    IEICE Transactions on Electronics 06/2012; E95.C(6):1086-1088. DOI:10.1587/transele.E95.C.1086 · 0.39 Impact Factor
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    Ji-Hun Eo, Sang-Hun Kim, Mun-Gyu Kim, Young-Chan Jang
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    ABSTRACT: A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18- 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.
    03/2012; 10(1). DOI:10.6109/jicce.2012.10.1.085
  • Han-Yeol Lee, Young-Chan Jang
    IEICE Electronics Express 01/2012; 9(23):1807-1812. DOI:10.1587/elex.9.1807 · 0.39 Impact Factor
  • Ji-Hun Eo, Sang-Hun Kim, Young-Chan Jang
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    ABSTRACT: A 200 kS/s 10-bit successive approximation (SA) analog-to-digital converter (ADC) with a rail-to-rail input signal is proposed for acquiring biosignals such as EEG and MEG signals. A split-capacitor-based digital-to-analog converter (SC-DAC) is used to reduce the power consumption and chip area. The SC-DAC's linearity is improved by using dummy capacitors and a small bootstrapped analog switch with a constant on-resistance, without increasing its area. A time-domain comparator with a replica circuit for clock feed-through noise compensation is designed by using a highly differential digital architecture involving a small area. Its area is about 50% less than that of a conventional time-domain comparator. The proposed SA ADC is implemented by using a 0.18-mu m 1-poly 6-metal CMOS process with a I V supply. The measured DNL and INL are +0.44/-0.4 LSB and +0.71/-0.62 LSB, respectively. The SNDR is 55.43 dB for a 99.01 kHz analog input signal at a sampling rate of 200 kS/s. The power consumption and core area are 5 mu W and 0.126 mm(2), respectively. The FoM is 47 fJ/conversion-step.
    IEICE Transactions on Electronics 11/2011; 94-C(11):1798-1801. DOI:10.1587/transele.E94.C.1798 · 0.39 Impact Factor
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    ABSTRACT: A bootstrapped analog switch with constant on-resistance is proposed for the successive approximation (SA) analog-to-digital converters (ADCs) that have many input-sampling switches. The initialization circuit, which is composed of a short pulse generator and a transmission gate, improves the linearity of the proposed bootstrapped analog switch by reducing the effect of the capacitive load. To evaluate the proposed bootstrapped analog switch, the 10-bit 1 MS/s CMOS SA ADC with a rail-to-rail differential input signal was designed by using a 0.18 mu m CMOS process with 1.0 V supply voltage. The proposed bootstrapped analog switch reduced the maximum V-GS variation of the conventional bootstrapped analog switch by 67%. It also enhanced the signal to noise-distortion ratio of the SA ADC by 4.8 dB when the capacitance of its gate node is 100 fF, and this improvement was maximized when the capacitance of its gate node increases.
    IEICE Transactions on Electronics 06/2011; 94-C(6):1069-1071. DOI:10.1587/transele.E94.C.1069 · 0.39 Impact Factor
  • Young-Chan Jang
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    ABSTRACT: A self-calibrating per-pin phase adjuster, which does not feedback from the slave chip and a multi-phase clock in the master and slave chips, is proposed for a high speed parallel chip-to-chip interface with a source synchronous double data rate (DDR) signaling. It achieves not only per-pin phase adjustment but also 90 phase shift of a strobe signal for a source synchronous DDR signaling. For this self-calibration, the phase adjuster measures and compensates the only relative mismatched delay among channels by utilizing on-chip time-domain reflectometry (TDR). Thus, variable delay lines, finite state machines, and a test signal generator are additionally required for the proposed phase adjuster. In addition, the power-gating receiver is used to reduce the discontinuity effect of the channel including parasitic components of chip package. To verify the proposed self-calibrating per-pin phase adjuster, the transceivers with 16 data, strobe, and clock signals for the interface with a source synchronous DDR signaling were implemented by using a 60 nm 1-poly 3-metal CMOS DRAM process with a 1.5 V supply. Each phase skew between Strobe and 16 Data was corrected within 0.028UI at I.6-Gb/s data rate in a point-to-point channel.
    IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences 02/2011; 94-A(2):633-638. DOI:10.1587/transfun.E94.A.633 · 0.23 Impact Factor
  • Young-Chan Jang
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    ABSTRACT: An unmatched source synchronous I/O link is proposed to reduce the time jitter of the sampling clocks for a receiver (RX) in a chip-to-chip interface system using a multi-phase clock. The proposed I/O link is initialized by two consecutive phase lock processes to optimize the RX sampling clocks. In the coarse lock process, the phase of the transmitted clock for a source synchronous I/O link is controlled by the resolution of the unit internal in the transmitter (TX) chip. The feedback path from the RX chip to the TX chip for the coarse lock information is merged into the normal path. The fine lock process is executed by a phase interpolator in the RX chip. The proposed I/O link reduces the latency and time jitter of RX sampling clocks by achieving the coarse lock process in the TX chip. To verify the proposed I/O link, a transceiver for a source synchronous I/O link clock with a quad data rate scheme was designed by using a 70 nm DRAM process with a 1.5 V supply. The proposed I/O link reduced the maximum jitter noise value by 42.4% in comparison to the jitter noise of a conventional multi-phase clock scheme.
    IEICE Electronics Express 06/2010; 7(11):797-803. DOI:10.1587/elex.7.797 · 0.39 Impact Factor
  • Young-Chan Jang
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    ABSTRACT: A swing level controlled voltage-mode transmitter is proposed to support a stub series-terminated logic channel with center-tapped termination. This transmitter provides a swing level control to support the diagnostic mode and improve the signal integrity in the absence of the destination termination. By using the variable parallel termination, the proposed transmitter maintains the constant output impedance of the source termination while the swing level is controlled. Also, the series termination using an external resistor is used to reduce the impedance mismatch effect due to the parasitic components of the capacitor and inductor. To verify the proposed transmitter, the voltage-mode driver, which provides eight swing levels with the constant output impedance of about 50Omega, was implemented using a 70nm 1-poly 3-metal DRAM process with a 1.5V supply. The jitter reduction of 54% was measured with the swing level controlled voltage-mode driver in the absence of the destination termination at 1.6-Gb/s.
    IEICE Transactions on Electronics 06/2010; 93-C(6):861-863. DOI:10.1587/transele.E93.C.861 · 0.39 Impact Factor
  • Young-Chan Jang
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    ABSTRACT: A digital phase corrector is proposed to reduce the time jitter noise in a high speed parallel chip-to-chip interface system with a quad data rate (QDR) input/output (I/O) scheme. The proposed digital phase corrector for the 4-phase clock utilizes only one duty cycle detector by using a digitally controlled phase correction method and multiplexing function of transmitter for a QDR I/O scheme. Also, it reduces the static phase error generated in the transmitter, because of the inclusion of a replica of the transmitter in the feedback loop. To verify the proposed digital phase correction scheme, a digital phase corrector for the QDR I/O scheme with a 1.25GHz 4-phase clock was designed by using a 70 nm 3-metal CMOS process with a 1.35V supply. The current consumption and phase correction range were 2.73mA and +/- 8%, respectively.
    IEICE Electronics Express 02/2010; 7(3):146-152. DOI:10.1587/elex.7.146 · 0.39 Impact Factor