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ABSTRACT: Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations within a functional block are compensated by the fine-grained supply voltage (V<sub>DD</sub>) control to minimize power at fixed clock frequency. In the 40-nm test chips, the layout of a data encryption core is divided into 6×7 voltage domains. Both high V<sub>DD</sub> (V<sub>DDH</sub>) and low V<sub>DD</sub> (V<sub>DDL</sub>) are supplied to each power domain and either V<sub>DDH</sub> or V<sub>DDL</sub> is adaptively selected according to the setup error warning signals generated by canary flip-flops. Compared with the conventional single V<sub>DD</sub> operation, the proposed FADVC reduced the power by 12% at 1-MHz clock in the measurement.
ESSCIRC (ESSCIRC), 2011 Proceedings of the; 10/2011
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ABSTRACT: Contention-less flip-flops (CLFF's) and separated power supply voltages (V<sub>DD</sub>) between flip-flops (FF's) and combinational logics are proposed to achieve a maximum energy efficiency operation. The proposed technologies were applied to a 16-bit integer unit (IU) for media processing in a 65-nm CMOS process. Measurement results of fabricated chips show that the proposed CLFF reduces the minimum operating voltage of IU's by 64mV on average. By scaling V<sub>DD</sub> from 1.2V to 310mV with the proposed CLFF, the maximum energy efficiency of 1835GOPS/W and the highest energy efficiency increase of 12.7 times are achieved.
Low Power Electronics and Design (ISLPED) 2011 International Symposium on; 09/2011
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ABSTRACT: In this paper we present an adaptive program-voltage generator for 3D-integrated solid state drives (SSDs) based on a boost converter. The converter consists of a spiral inductor, a high-voltage MOS circuit, and an adaptive-frequency and duty-cycle (AFD) controller. The spiral inductor requires an area of only 5 × 5 mm<sup>2</sup> in an interposer. The high-voltage MOS circuit employs a mature NAND flash process. The AFD controller, implemented in a conventional low-voltage MOS process, dynamically optimizes clock frequencies and duty cycles at different values of output voltage, V<sub>OUT</sub>. The power consumption, rising time, and circuit area of the program-voltage generator are 88%, 73%, and 85% less than those of a program-voltage generator with a conventional charge pump, respectively. The total power consumption of each NAND flash memory is reduced by 68%. We also present the design methodology of the high-voltage MOS circuit of the boost converter with a conventional NAND flash process, in which charge-pump-based program-voltage generators are implemented.
IEEE Journal of Solid-State Circuits 07/2011; · 3.23 Impact Factor
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ABSTRACT: Clock skew is a major cause of severe timing yield degradation for sub-/near-threshold digital circuits. We report for the first time on employing hot-carrier injection (HCI) for post silicon clock-deskew trimming. An HCI trimmed clock buffer, which can be individually selected and stressed to adjust the clock edge, is proposed. In addition, it can be used in conjunction with on-chip skew monitoring circuits to achieve auto-stressing. Our approach is proven to be effective through a representative 1.1-mm × 0.8-mm clock tree in a 40-nm high-k complimentary metal-oxide-semiconductor process. On average, it reduces the clock skew by eight times at 0.4 V V<sub>dd</sub>. No significant recovery is noticed two weeks after trimming.
Circuits and Systems II: Express Briefs, IEEE Transactions on 06/2011; · 1.41 Impact Factor
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ABSTRACT: A 3-D solid-state drive system with through-silicon via (TSV) technology and boost converter is presented in this paper. The proposed boost converter enables the supply voltage reduction to 1.8 V and smaller NAND Flash memory chips. From the simulation results, the conventional bonding-wire technology can achieve only eight NAND chip integrations not only due to their structural problem but also due to the performance degradation. On the other hand, 128 NAND Flash memory chips can be integrated into a package with full-copper TSVs and the proposed system has about 1.70 μs of rise time for 20 V, 74.2 nJ of the energy dissipation, and 225 μm<sup>2</sup> of additional Si area consumption for a NAND chip. Even if poly-Si TSVs are used, because of the process restriction, 64 NAND chips can be stacked with about 34% longer rise time and 22% degradation of energy dissipation compared to a full-copper TSV by grinding the Si-substrate to 10 μm .
IEEE Transactions on Components, Packaging, and Manufacturing Technology 03/2011; · 0.98 Impact Factor
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Yu Pu,
Xin Zhang,
J. Huang,
A. Muramatsu,
M. Nomura,
K. Hirairi,
H. Takata,
T. Sakurabayashi,
S. Miyano, M. Takamiya,
T. Sakurai
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ABSTRACT: Many of us in the field of ultra-low-V<sub>dd</sub> processors experience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper investigates five major pitfalls which are often not appreciated by researchers when claiming that their circuits outperform others by working at a lower V<sub>dd</sub> with a higher energy-efficiency. These pitfalls include: i) overlook the impacts of different technologies and different V<sub>th</sub> definitions, ii) only emphasize energy reduction but ignore severe throughput degradation, or expect impractical pipelining depth and parallelism degree to compensate this throughput degradation, iii) unrealistically assume that memory's V<sub>dd</sub> and energy could scale as well as standard cells, iv) use the highest temperature as the worst timing corner as in the super-threshold, but in fact negative temperature becomes much more detrimental in the sub/near threshold regime, v) pursue just-in-need V<sub>dd</sub> to compensate effects of PVT, but without considering the high energy loss on DC-DC converters. Therefore, the actual energy benefit from using a sub/near threshold V<sub>dd</sub> can be greatly overestimated. This work provides some design guidelines and silicon evidence to ultra-low-V<sub>dd</sub> systems. The outlined pitfalls also shed light on future directions in this field.
Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
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ABSTRACT: To effectively reduce output ripple of switched-capacitor DC-DC converters which generate variable output voltages, a novel feedback control scheme is presented. The proposed scheme uses pulse density and width modulation (PDWM) to reduce the output ripple with low output voltage. The prototype chip was implemented using 65nm CMOS process. The switched-capacitor DC-DC converter has 0.2-V to 0.47-V output voltage and delivers 0.25-mA to 10-mA output current from a 1-V input supply with a peak efficiency of 87%. Compared with the conventional pulse density modulation (PDM), the proposed switched-capacitor DC-DC converter with PDWM reduces the output ripple by 57% in the low output voltage region with the efficiency penalty of 2%.
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian; 12/2010
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ABSTRACT: In this paper, a 0.18-V input three-stage charge pump circuit applying forward body bias is proposed. In the developed charge pump, all the MOSFETs are forward body biased by using the inter-stage/output voltages. By applying the proposed charge pump as the startup in the boost converter, the lower kick-up input voltage of the boost converter can be achieved. To verify the circuit characteristics, four test circuits have been implemented by using 65nm CMOS process. The measured available output current of the proposed charge pump under 0.18-V input voltage can be improved more than 150%. In addition, the boost converter can successfully been boosted from 0.18-V input to the 0.74-V output under 6mA output current. The proposed circuit is suitable for extremely low voltage applications such as harvesting energy sources.
Custom Integrated Circuits Conference (CICC), 2010 IEEE; 10/2010
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ABSTRACT: Digital LDO is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-μA quiescent current at 200-μA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.
Custom Integrated Circuits Conference (CICC), 2010 IEEE; 10/2010
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ABSTRACT: This paper investigates the effect of the TSV resistance (R<sub>TSV</sub>) on the performance of boost converters for Solid State Drive (SSD) using circuit simulation. When R<sub>TSV</sub> is 0 Omega, both the rising time (t<sub>rise</sub>) from 0 V to 15 V and the energy during boosting (E<sub>loss</sub>) of the output voltage (V<sub>OUT</sub>) are 10.6% and 6.6% of the conventional charge pump respectively. In contrast, when R<sub>TSV</sub> is 200 Omega, for example, t<sub>rise</sub> is 30.1% and E<sub>loss</sub> is 22.8% of the conventional charge pump. Besides, V<sub>OUT</sub> cannot be boosted above 20 V when R<sub>TSV</sub> is larger than 210 Omega. Therefore, in order to maintain the advantages of the boost converter over the charge pump in terms of t<sub>rise</sub> and E<sub>loss</sub>, the reduction of R<sub>TSV</sub> is very important.
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on; 10/2009
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ABSTRACT: A low-power program-voltage generator (PVG) using a boost converter with an adaptive-frequency and duty-cycle (AFD) controller is implemented. SSD consists of the HVMOS chip (0.35 x 0.50 mm<sup>2</sup>), the AFD controller chip (0.67 x 0.28mm2), a 270nH 0.5Omega inductor in an interposer (5 x 5mm<sup>2</sup>), and a 56 nm 16 Gb NAND Flash memory chip.
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International; 03/2009
