ABSTRACT: In this paper, the authors present an event-driven system with resources to run applications with different degrees of complexity in an energy-aware way. The architecture uses effective system partitioning to enable duty cycling, SIMD instructions, power gating, voltage scaling, multiclock domains, multivoltage domains, and extensive clock gating. The system has sufficient computational power to run a complex ECG algorithm with feature extraction and motion artifact cancellation or multichannel EEG processing. The system consumes an average of 13 pJ/cycle running a CWT-based ECG application at 0.4 V. The processor can run at voltage range of 0.4 to 1.2 V and supports frequency range of 1 to 100 MHz. The system has comparable energy/cycle, more computation capability, and larger available frequencies than the previously reported complex designs in the works of Sindhara et al.  and Chen et al. .
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International; 03/2011