C.D. Presti

University of California, San Diego, San Diego, California, United States

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Publications (28)22.24 Total impact

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    ABSTRACT: In many base-station applications, the load/usage fluctuates over time periods of hours to days, thereby varying the required transmit power by as much as 10 dB. It is desirable to maintain high efficiency and linearity in the power amplifier under these back-off conditions in order to achieve high long-term efficiency. This paper demonstrates a scalable digital predistortion (DPD) approach that can be applied under different power back-off levels in envelope-tracking (ET) amplifiers and quantifies the associated efficiency. Efficiency comparisons are made with other amplifier configurations such as Class B and Doherty. Efficiency of 60% at full power (35 W average power) and >30% efficiency at 10 dB average power back-off are measured in an ET amplifier with a 7.54 dB peak-to-average ratio (PAPR) single-carrier WCDMA signal while meeting linearity specifications. Long-term base-station usage probability functions are presented. The long-term efficiency of the ET amplifiers is simulated to be greater than that of Class B and Doherty amplifiers.
    International Journal of Microwave and Wireless Technologies 04/2013; 5(02). · 0.57 Impact Factor
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    ABSTRACT: A high-performance bipolar-CMOS-DMOS (BCD) monolithic envelope amplifier for micro-base-station power amplifiers (PAs) is presented. Measurement of the BCD high-voltage (VDD = 15 V) envelope amplifier shows an efficiency of 72% using 7.7-dB peak-to-average ratio WCDMA input signals at an average envelope amplifier output power above 3 W. A WCDMA envelope-tracking RF PA at 2.14 GHz, including a GaN field-effect transistor RF stage, has an overall drain efficiency above 51%, with a normalized power root-mean-square error below 1.2% and an adjacent channel leakage ratio of -49 dBc at 5-MHz offset using memory-effect mitigation digital pre-distortion, at an average output power above 2 W and a gain of 10 dB.
    IEEE Transactions on Microwave Theory and Techniques 06/2012; 60(6):1850-1861. · 2.23 Impact Factor
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    ABSTRACT: Envelope tracking provides the potential for achieving high efficiency in power amplifiers for next generation wireless systems with high peak-to-average ratio signals such as LTE. Envelope modulators with low cost, high efficiency and wide bandwidth are critical enablers for the widespread application of ET. This presentation reviews the development of various Si ICs for ET applications in basestation PAs and in handset PAs. Requirements of voltage swing, bandwidth, and accuracy are first described. BCD technology-based Si ICs for envelope modulators achieving voltages as high as 50V are presented, for operation in basestations with LDMOS and GaN RF power transistors. CMOS-based Si envelope modulator ICs for operation in wireless handsets are also discussed. ET amplifiers that achieve overall efficiency as high as 45% in 20MHz LTE handset applications are presented.
    01/2012;
  • C.D. Presti, D.F. Kimball, P.M. Asbeck
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    ABSTRACT: A real-time adaptive digital predistortion system (RT-ADPD) for power amplifier linearization is described in this paper, featuring fast closed-loop adaptation to provide robust linearity across quickly shifting power amplifier (PA) operating conditions. The RT-ADPD system requirements, architecture, and its design methodology are analyzed in detail, with particular emphasis on the optimization of the feedback loop convergence speed and stability. A novel, compact algorithm to achieve rapid adaptation of the predistortion lookup tables, without any prior knowledge of the PA distortion characteristics, is introduced. A prototype of the RT-ADPD system is implemented using a field-programmable gate array (FPGA), and it is experimentally exploited to linearize a handset WCDMA PA module. Due to the linearization action, the PA maximum modulated output power is increased by 1.9 dB, to 30.9 dBm, and its power-added efficiency by 9%, to 48.5%, still maintaining a -40-dB ACPR at a 5-MHz offset. In addition, a true closed-loop adaptation ensures excellent PA linearity under load mismatch and other environmental variations. Indeed, ACPR is improved by up to 15 dB, below -47 dB, under 2:1 VSWR at 28 dBm. Remarkably fast adaptation speed is also demonstrated, as adequate signal fidelity is achieved within a ~50-μs time frame.
    IEEE Transactions on Microwave Theory and Techniques 01/2012; 60(3):604-618. · 2.23 Impact Factor
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    ABSTRACT: An attenuator is presented in a 0.13 μm silicon-on-insulator (SOI) CMOS technology, to be used for power control of RF wireless transmitters. The design is based on a T-network consisting of two series switches and 63 shunt switches. A gate switching technique is utilized in the series switches for high power handling and high isolation. Measurements at 1.88 GHz show that the minimum insertion loss is as low as 0.6 dB and maximum attenuation is 55.3 dB with worst input return loss of 8.1 dB. The attenuation can be digitally controlled in steps of around 1 dB. The 1 dB gain compression point is as high as 21.0 dBm in the through mode.
    IEEE Microwave and Wireless Components Letters 09/2011; · 1.78 Impact Factor
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    ABSTRACT: This paper presents a high performance BCD (Bipolar-CMOS-DMOS) monolithic envelope tracking IC to achieve high efficiency and linearity for micro-base station power amplifier applications. Measurement of the BCD high voltage (Vdd = 15 V) envelope amplifier shows an efficiency of 72% using WCDMA input signals (7.7 dB PAR). An envelope tracking power amplifier including a GaN FET RF stage has overall drain efficiency (DE) above 51%, with a normalized power RMS error below 1.2% and ACLR1 of -49 dBc using memory mitigation digital pre-distortion (DPD), at an average WCDMA output power above 2 W and a gain of 10 dB.
    Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE; 07/2011
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    ABSTRACT: This letter presents a 44 GHz GaAs MMIC-based power amplifier (PA) which uses envelope tracking (ET) techniques for efficiency enhancement. Digital pre-distortion (DPD) is also employed to achieve high linearity. For a 7.6 dB PAPR 64QAM 20 MHz bandwidth signal (data rate 120 Mb/s) at an output power of 23.8 dBm, the measured EVM was 2.0% and ACPR1 was better than -40 dBc. Power efficiency enhancement of more than 5.7 times for the final MMIC stage (from 1.22% to 7%) was measured, using an external drain modulator. To the authors' best knowledge, this is the first time envelope tracking has been applied to PAs in the millimeter wave regime.
    IEEE Microwave and Wireless Components Letters 04/2011; · 1.78 Impact Factor
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    ABSTRACT: Adaptive Digital Predistortion (DPD) is applied to a spec-compliant class-AB GaAs HBT PA module for WCDMA handsets. It is shown that, by using a re-optimized load line, the efficiency can be increased from 37.5% to 47% at nominal 28.5 dBm output power, while maintaining the same excellent linearity of the original PA. The quiescent current consumption is also reduced down to 40 mA at all power levels, enabling up to 49% average dc power savings without dynamic biasing. Under 2:1 VSWR, 7% to 11% higher PAE is demonstrated at 28 dBm, achieving significant ACPR reduction as well. The methodology to tradeoff the linearization capability of DPD to optimize efficiency at a specified power and linearity is discussed in detail.
    Microwave Symposium Digest (MTT), 2010 IEEE MTT-S International; 06/2010
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    ABSTRACT: A UHF RFID rectifier which turns on at near zero input voltage is demonstrated. The rectifier is fabricated in 0.25-μm silicon-on-sapphire (SOS) CMOS technology using intrinsic, near zero threshold devices. A novel improved cross-coupled bridge topology is used to minimize the leakage incurred through the use of intrinsic devices while maintaining their low power turn on characteristics. The fabricated rectifier demonstrates a peak power conversion efficiency (PCE) of 71.5% at 915 MHz with a RF input of -4 dBm and a 30 kΩ load. More importantly, a PCE > 30% was measured for all RF input powers between -28 and -4 dBm demonstrating state-of-the-art efficiency across a wide range of input powers.
    Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE; 06/2010
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    ABSTRACT: A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-??m 2.5-V standard I/O FETs in a 0.13-??m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.
    IEEE Transactions on Microwave Theory and Techniques 02/2010; · 2.23 Impact Factor
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    ABSTRACT: RF power transistors are typically operated at extreme drain voltage and current peaks, which cause severe impact ionization conditions at the channel pinch-off region. On a SOI CMOS technology platform, the resulting large body currents may eventually lead to single transistor latch-up, unless the length of the gate/body finger is properly chosen.In this work, the effect of single-transistor latch-up on the large-signal performance of SOI CMOS RF power transistors is investigated for the first time. Extensive multi-harmonic load–pull measurements have been performed to characterize the resulting current runaway phenomenon and its detrimental effect on the device efficiency. Useful guidelines have been derived to avoid such limitations and a prototype power transistor has been designed accordingly. Thanks to the proposed design criteria, the device achieves latch-up-free operation at the nominal 2-V supply voltage, while exhibiting an excellent 72% power-added efficiency at a 19.5-dBm output power level under 1.9-GHz continuous-wave excitation.Moreover, an experimental study on the gate oxide degradation kinetics under RF stress has been carried out to characterize the long-term device reliability of the adopted SOI CMOS process.
    Solid-State Electronics 01/2010; · 1.48 Impact Factor
  • F. Carrara, C.D. Presti, G. Palmisano
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    ABSTRACT: In this work, the potential of load adaptation for enhanced back-off efficiency in RF power amplifiers (PAs) is investigated through a 0.13-mum silicon-on-insulator (SOI) CMOS fabrication technology. To this aim, the first CMOS PA with fully integrated reconfigurable output matching network is presented. The PA delivers a 24-dBm maximum output power while operating at 2.4 GHz and 2-V supply voltage. A significant efficiency improvement of up to 34% is achieved through load adaptation, peak efficiency being as high as 65%. Linear operation is also demonstrated under two-tone excitation, since a 16-dBm output power is attained while complying with a -40-dBc IM3 specification.
    ESSCIRC, 2009. ESSCIRC '09. Proceedings of; 10/2009
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    ABSTRACT: In this work, the RF power performance of a 0.13-mum partially depleted SOI CMOS technology is explored. To this end, a prototype 1-mm-width power transistor has been designed and fabricated for multi-harmonic load-pull characterization. The device tolerance to single-transistor latch-up under large-signal conditions has been considered as the key design issue for safe operation in RF power applications. Proper design criteria have been derived and the length of the gate fingers has been chosen accordingly. The test device achieves a 72% power-added efficiency and a 19.5-dBm output power level, while operating at a 2-V supply voltage under 1.9-GHz continuous-wave excitation.
    Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European; 10/2009
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    ABSTRACT: In this paper, the potential of load adaptation for enhanced backoff efficiency in RF power amplifiers (PAs) has been investigated through a 0.13-mum silicon-on-insulator (SOI) CMOS fabrication technology. The RF power performance of the adopted SOI CMOS process has been preliminarily characterized by on-wafer load-pull measurements on a custom unit power transistor. A 2.4-GHz 24-dBm 2-V SOI CMOS PA with fully integrated reconfigurable output matching network has then been designed and experimentally characterized. A significant efficiency improvement of up to 34% has been achieved through load adaptation, peak efficiency being as high as 65%. Linear operation has also been demonstrated under two-tone excitation, as a 16-dBm output power has been attained while complying with a - 40-dBc third-order intermodulation distortion specification.
    IEEE Transactions on Microwave Theory and Techniques 10/2009; · 2.23 Impact Factor
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    ABSTRACT: A digitally modulated power amplifier (DPA) in 1.2 V 0.13 mum SOI CMOS is presented, to be used as a building block in multi-standard, multi-band polar transmitters. It performs direct amplitude modulation of an input RF carrier by digitally controlling an array of 127 unary-weighted and three binary-weighted elementary gain cells. The DPA is based on a novel two-stage topology, which allows seamless operation from 800 MHz through 2 GHz, with a full-power efficiency larger than 40% and a 25.2 dBm maximum envelope power. Adaptive digital predistortion is exploited for DPA linearization. The circuit is thus able to reconstruct 21.7 dBm WCDMA/EDGE signals at 1.9 GHz with 38% efficiency and a higher than 10 dB margin on all spectral specifications. As a result of the digital modulation technique, a higher than 20.1 % efficiency is guaranteed for WCDMA signals with a peak-to-average power ratio as high as 10.8 dB. Furthermore, a 15.3 dBm, 5 MHz WiMAX OFDM signal is successfully reconstructed with a 22% efficiency and 1.53% rms EVM. A high 10-bit nominal resolution enables a wide-range TX power control strategy to be implemented, which greatly minimizes the quiescent consumption down to 10 mW. A 16.4% CDMA average efficiency is thus obtained across a > 70 dB power control range, while complying with all the spectral specifications.
    IEEE Journal of Solid-State Circuits 08/2009; · 3.06 Impact Factor
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    ABSTRACT: A single-stage stacked-FET power amplifier (PA) is demonstrated using a 0.28-mum silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. The stacked-FET PA has been designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. The measurement results show that, with a 6.5-V supply, the PA achieves a small-signal gain of 13.2 dB, a saturated output power of 33 dBm, and a maximum power-added-efficiency (PAE) of 47% at 1.9 GHz. This is the first reported stacked-FET PA in submicron SOI CMOS technology that delivers multi-Watt output power in the GHz range. It also maintains high power efficiency over a wide range of supply voltages.
    Microwave Symposium Digest, 2009. MTT '09. IEEE MTT-S International; 07/2009
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    ABSTRACT: A single-ended digitally-modulated power amplifier (DPA) is demonstrated in a 0.13-mum 1.2-V SOI CMOS technology, to be used in a multistandard RF polar transmitter. The amplitude modulation is done by digitally controlling the number of activated unit amplifiers whose currents are summed at the output. The DPA is designed for multi-mode multi-band functionality by avoiding frequency-selective components, except for the final-stage output matching network. The measured DPA is fully functioning and reliably delivers a 24.9-dBm peak output power at 900 MHz with a maximum power efficiency of 62.7%. It also exhibits similar high-efficiency performance for other carrier frequencies with a reconfigured matching network.
    Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE; 07/2009
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    ABSTRACT: Design techniques for handset power amplifiers are discussed, with emphasis on high efficiency architectures and CMOS technology. Experimental results with prototype circuits including Doherty, envelope tracking, outphasing and digital polar modulation are presented. Future design challenges are also highlighted.
    Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09. IEEE Topical Meeting on; 02/2009
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    ABSTRACT: A transceiver front-end for 5 GHz wireless local area network applications has been designed and implemented in a low-cost 46 GHz f<sub>T</sub> pure-silicon bipolar technology. The transceiver front-end adopts a superheterodyne sliding-IF architecture and consists of a down-converter, an up-converter and an LO frequency synthesiser. By exploiting a 1 bit variable-gain low-noise amplifier, the down-converter is able to provide an excellent noise figure of 4 dB while ensuring an input 1 dB compression point of -10 dBm with a current consumption of 25 mA from a 3 V supply voltage. The transmitter front-end is implemented by means of a current-reuse variable-gain up-converter. The circuit provides an output 1 dB compression point of 5.3 dBm although consuming only 45 mA from a 3 V supply voltage. Moreover, a linear-in-dB gain control characteristic is achieved over a 35 dB dynamic range. The LO frequency synthesiser is implemented by means of an integer-N phase-locked loop. It features a phase noise of -117 dBc/Hz at 1 MHz offset from the centre frequency of 4.1 GHz and exhibits a tuning range of 1.2 GHz, from 3.47 to 4.65 GHz. The LO frequency synthesiser draws 20 mA from a 3 V supply voltage.
    IET Circuits Devices & Systems 11/2008; · 1.02 Impact Factor
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    ABSTRACT: A digitally-controlled power amplifier (DPA) in 0.13-mum 1.2-V SOI-CMOS is demonstrated, to be used as a building block in a multi-standard radio transmitter. The circuit performs direct amplitude modulation of an input RF carrier, by digitally controlling a large array of RF gain cells. It exhibits a 24.5-dBm peak output power at 1.9 GHz, and an effective resolution better than 7 bits. A novel two-stage topology for the gain cell is described, which allows the DPA to seamlessly operate from 800 MHz through 2 GHz, with a full-power efficiency larger than 40% and a small-signal gain of 14.5 dB. A new strategy is also proposed to provide a wide-range transmit power control.
    Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European; 10/2008