K. Tomko

Publications (5)1.47 Total impact

• Conference Proceeding: Design of a Scalable InfiniBand Topology Service to Enable Network-Topology-Aware Placement of Processes

  H Subramoni, S Potluri, K Kandalla, B Barth, J Vienne, J Keasler, K Tomko, K Schulz, A Moody, D K Panda
  Supercomputing 2012, Best Paper Finalist; 11/2012
• Source

  Available from: Jérôme Vienne

  Conference Proceeding: Can Network-Offload based Non-Blocking Neighborhood MPI Collectives Improve Communication Overheads of Irregular Graph Algorithms?

  K Kandalla, A Buluc, H Subramoni, K Tomko, J Vienne, L Oliker, D K Panda
  International Workshop on Parallel Algorithms and Parallel Software (IWPAPS 2012), to be held in Conjunction with IEEE Cluster 2012; 09/2012
• Conference Proceeding: Designing Non-blocking Allreduce with Collective Offload on InfiniBand Clusters: A Case Study with Conjugate Gradient Solvers Int'l Parallel and Distributed Processing Symposium

  K Kandalla, U Yang, J Keasler, T Kolev, A Moody, H Subramoni, K Tomko, J Vienne, D K Panda
  IPDPS'12; 05/2012
• Article: Codesign for InfiniBand Clusters

  S. Sur, S. Potluri, K.C. Kandalla, H. Subramoni, D.K. Panda, K. Tomko
  [show abstract] [hide abstract]
  ABSTRACT: Codesigning applications and communication libraries to leverage underlying network features is imperative for achieving optimal performance on modern computing clusters.
  Computer 12/2011; · 1.47 Impact Factor
• Source

  Available from: psu.edu

  Conference Proceeding: A prototype FPGA finite-difference time-domain engine for electromagnetics simulation

  R. Culley, A. Desai, S. Gandhi, Shugaung Wu, K. Tomko
  [show abstract] [hide abstract]
  ABSTRACT: Several field-programmable gate array (FPGA) based reconfigurable high-performance computing systems have recently become available. In this paper we describe our experience developing an application accelerator for a traditional HPC application, a finite-difference time-domain (FDTD) electromagnetics simulation, for two such systems. We describe the design of our FDTD calculation engine and demonstrate that FPGA can accelerate a single precision floating point implementation. We discuss the current limitations of our design and describe design improvements to overcome them.
  Circuits and Systems, 2005. 48th Midwest Symposium on; 09/2005