Mutsuko Hatano

Tokyo Institute of Technology, Edo, Tōkyō, Japan

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Publications (38)36.8 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: The behavior of the subthreshold slope (SS) of fully depleted (FD) amorphous In-Ga-Zn-O (a-InGaZnO) thin-film transistors (TFTs), which are n-type accumulation mode metal-oxide-semiconductor transistors, was analyzed. Thermal desorption spectra revealed that annealing was necessary to desorb H2 and H2O from the a-InGaZnO films for the FD mode operation along with small SS. Our experimental results indicated that the SS (a) increases with the increase in the thickness of the a-InGaZnO channel layer, (b) increases with the decrease in the oxygen partial pressure during the sputtering of the a-InGaZnO, (c) increases linearly with the increase in the thickness of the gate insulator, and (d) increases linearly with the increase in the temperature of the TFT. A theoretical equation that explains these results was derived by using the relations between the variations in the voltages applied to the electrodes and variations in the surface potentials derived from the charge conservation law. It was assumed during the derivation of the equation that the potential in the channel layer is the lowest along the back surface in the subthreshold region and most of the current flows there.
    Applied Physics Letters 01/2015; 106(1):013504. DOI:10.1063/1.4905469 · 3.52 Impact Factor
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    ABSTRACT: Trial production of a thin-film radio frequency identification (RFID) tag with a built-in antenna was carried out using an amorphous InGaZnO (a-InGaZnO) thin-film transistor (TFT). A rectifier circuit, RF communication circuit, and logic circuit were formed using an a-InGaZnO TFT. Even after adding an antenna, which is the thickest part, the RFID itself had a thickness of about 1 μm. The RFID operated with a 13.56-MHz-band reader for IC cards and near field communication (NFC) devices. These results indicate the feasibility of an RFID tag that can be adhered to objects with a variety of shapes.
    2014 21st International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD); 07/2014
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    ABSTRACT: We investigate the relationship between the defect states and the carrier transport property of Si nanostructure-based solar cells. The solar cell consists of a Schottky junction including Si/SiO2 multiple quantum wells. The carrier transport is significantly enhanced by forming gas annealing of Si/SiO2 multiple quantum wells, which is well correlated with the decrease in the Pb and E′ center densities evaluated by electron spin resonance. In particular, we find that high temperature (>600 °C) annealing is necessary to passivate E′ center. Our results demonstrate the significance of defect passivation for the realization of high efficiency Si nanostructure-based solar cells.
    Applied Physics Letters 10/2012; 101(15). DOI:10.1063/1.4758473 · 3.52 Impact Factor
  • MRS Online Proceeding Library 01/2011; 685. DOI:10.1557/PROC-685-D4.3.1
  • MRS Online Proceeding Library 01/2011; 621. DOI:10.1557/PROC-621-Q7.6.1
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    ABSTRACT: The temperature dependence of the performance and hot-carrier instability of excimer-laser-crystallized low-temperature polycrystalline silicon thin-film transistors (TFTs) is described. The dependence of the TFT's performance on temperature indicates three characteristics: 1) electron mobility decreases with decreasing temperature, whereas the hole mobility is temperature independent; 2) off-leakage current decreases with decreasing temperature; and 3) threshold voltage increases with decreasing temperature. To consider the origin of the temperature dependence of the threshold voltage, estimation using the trap state density obtained by capacitance-voltage analysis is carried out. The main origin is concluded to be the change in the density of occupied defect states owing to the temperature dependence of the Fermi level. Contrary to the mobility, current under the drain-avalanche hot-carrier stress is found to be higher in a cold environment. The more serious current degradation after the stress in a cold environment is attributable to the reduced scattering of hot carriers owing to less lattice vibration.
    Japanese Journal of Applied Physics 08/2010; 49(8). DOI:10.1143/JJAP.49.084101 · 1.06 Impact Factor
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    ABSTRACT: We have developed bottom-gate amorphous-oxide TFTs with ZTO/ITO channel layers. The fabricated ZTO/ITO-TFTs demonstrated that threshold voltage (Vth) dispersion for TFTs with channel thickness dispersion was smaller one order of magnitude than that of conventional TFTs. Afield effect mobility of 52 cm2/Vs was obtained.
    05/2010; 41(1). DOI:10.1889/1.3499904
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    ABSTRACT: The degradation characteristics of n- and p-channel polysilicon thin-film transistors (TFTs) under circuit operation were investigated by using CMOS inverter circuits consisting of n-channel TFTs with a lightly doped drain (LDD) structure and p-channel TFTs with a single-drain (SD) structure. A new test element made it possible to separately evaluate the degradation characteristics of each type of TFT during CMOS inverter operation. In regard to n-channel LDD TFTs, the device degradation is mainly caused by accumulated dc stress under the condition that the gate voltage is near the threshold voltage and the high drain voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress condition. In p-channel SD TFTs, the device degradation is caused by the mutual interaction between DAHC stress and negative-bias-temperature (NBT) stress. Hole injection due to NBT stress is accelerated by DAHC-stress-induced trapped electrons under inverter-circuit operation. The effect is thus enhanced not only by the increase in the number of hole injections but also by the increase in the number of electron injections. It was found that the device characteristics of p-channel TFTs are more rapidly degraded as the rising time of the input pulse becomes shorter. This degradation is caused by the transient increase in the number of hot electrons, which are generated when holes are emitted from the trap states when the p-channel TFTs are turned off.
    IEEE Transactions on Electron Devices 03/2010; DOI:10.1109/TED.2009.2036808 · 2.36 Impact Factor
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    ABSTRACT: — A flexible-printed-cable (FPC) free liquid-crystal-display (LCD) panel by using a capacitive-coupling technique has been developed. A QQVGAeight-color image was successfully displayed for the first time without attaching any signal or power cables to the panel. The receiving circuitry and capacitive-coupling electrodes were integrated on the LCD panel using a low-temperature polysilicon (LTPS) fabrication process. In the proposed digital coding method, the receiving circuit converts derivative waveform signals via the capacitive coupling to conventional logic-level signals. The maximum data rate of 2.4-Mbps × 3ch (RGB) was achieved. In addition, LTPS low-capacitance diode bridge and regulator enabled us to obtain stable DC power of 2.4 mW on the panel from the AC-power signal. This study is the first step towards integrating the wireless-communication function on the display panel to achieve a high-value-added flat-panel display (FPD).
    01/2010; 18(6). DOI:10.1889/JSID18.6.454
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    ABSTRACT: A model for predicting on-current degradation caused by drain-avalanche hot carriers in NMOS low-temperature polysilicon thin-film transistors (TFTs) is described. The amount of trapped charge caused by hot-carrier stress was estimated by using a model describing the lightly doped drain region as an imaginary TFT, and it was found that the amount of trapped charge saturates as voltage-stress time passes. Moreover, the on-resistance increase caused by the trapped charge could be expressed as a function of voltage-stress time (t) , stress drain current (I<sub>d_str</sub>), and stress drain voltage (V<sub>d_str</sub>), i.e., DeltaR<sub>on</sub> = I<sub>d_str</sub> exp(-beta/ V<sub>d_str</sub>) At<sup>B</sup>. This function can be used to predict the on-current degradation of TFTs after a long time for various gate lengths, operation voltages, and crystallinities of polysilicon.
    IEEE Transactions on Electron Devices 02/2009; 56(1-56):109 - 115. DOI:10.1109/TED.2008.2008376 · 2.36 Impact Factor
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    ABSTRACT: The hysteresis behavior in p-type poly-Si TFTs causes malfunctions in analog circuits. To analyze the hysteresis, we adopted the On-the-Fly measurement that was used in the analyses of the negative bias temperature instability of Si LSIs. We modified the measurement for poly-Si TFTs and monitored the hole trapping from the fully detrapped states in order to quantitatively evaluate the hysteresis. A TFT annealed at 550oC had smaller trapping than a TFT annealed at 490oC due to fewer Si-OH bonds.
    ECS Transactions 10/2008; 16(9). DOI:10.1149/1.2980537
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    ABSTRACT: A polysrystalline silicon (poly-Si) layer prepared by selectively enlarging laser crystallization (SELAX) was post-annealed by excimer laser irradiation. The average grain width increased 26% because of partly merged grains, while the morphological trace of the laterally grown poly-Si layer was maintained. The difference in field-effect mobility resulting from thin-film-transistor (TFT) configuration was reduced by post-annealing. The field-effect mobility of TFTs parallel to the lateral growth direction decreased slightly (within 4.5% for n-type and 11.5% for p-type). On the other hand, TFTs configured perpendicular to the lateral growth direction increased as the energy density during post-annealing increased (up to 200% for both types). For n-type TFTs these results were attributed to the increase of the effective width of the grain and the reduction of the density of trapping states at grain boundaries.
    Japanese Journal of Applied Physics 08/2008; 47(8):6217-. DOI:10.1143/JJAP.47.6217 · 1.06 Impact Factor
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    ABSTRACT: We have developed a FPC-free LTPS-LCD panel with capacitive coupling and displayed a QQVGA-eight color static image for the first time, by utilizing our proposed digital coding architecture and LTPS low capacitance diode-bridge. The maximum data-rate of 2.4 Mbps × 3ch(RGB) and the power of 2.5 mW on the panel were obtained.
    SID Symposium Digest of Technical Papers 01/2008; 39(1). DOI:10.1889/1.3069833
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    ABSTRACT: The degradation mechanism in p-channel polysilicon thin-film transistors under negative-bias temperature (NBT) stress and pulse stress, which alternates NBT stress and drain-avalanche hot carrier (DAHC) stress, was investigated. An analysis of recovery effects and activation energy suggests that the device degradation under dc-NBT stress is explained by a reaction-diffusion model and limited by hydrogen diffusion. These features are also observed in the case of the device degradation under pulse stress. Pronounced degradation occurs not after DAHC stress application (electron injection) but after NBT stress application (hole injection). NBT stress degradation is locally accelerated after DAHC stress application because the effective gate voltage negatively increases due to trapped electrons during DAHC stress. The trap states and positive charges that were generated by this accelerated NBT stress are considered to be the main cause of device degradation under pulse stress.
    IEEE Transactions on Electron Devices 10/2007; 54(9-54):2452 - 2459. DOI:10.1109/TED.2007.901878 · 2.36 Impact Factor
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    ABSTRACT: The device performance and reliability of the SOI TFTs and the LTPS-TFTs were compared. Changing channel material from single-crystal Si to ELA poly-Si reduces mobility by 75%, and changing gate oxide material from thermal oxide to CVD oxide enhances current degradation due to hot carrier stress by almost ten times. To improve performance, selectively enlarging laser crystallization (SELAX) process which realizes poly-Si films with large grain and smooth surface has been developed. The mobility of SELAX-TFTs is twice of conventional LTPS-TFTs. To fabricate high quality interfacial layer at the interface between the gate oxide layers and the channel layers, cyclic deposition with O2 plasma treatment (C-DOP) process has been also developed. The lifetime of hot carrier degradation was extended by tenth using the C-DOP process.
    ECS Transactions 07/2007; 8(1). DOI:10.1149/1.2767283
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    ABSTRACT: A unified model and a prediction technique for on-current degradation in NMOS low-temperature poly-Silicon thin-film transistors are presented. The resistance increase is expressed as a function of the stress-drain current and stress-drain voltage. This function is independent of the size, crystallinity, or initial characterization of the transistors. The turnaround time for circuit design can be shortened by using this technique.
    SID Symposium Digest of Technical Papers 05/2007; 38(1). DOI:10.1889/1.2785264
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    ABSTRACT: Narrow frame size IPS-mode LCD with high resolution system-in- display have been developed utilizing hybrid laser crystallization technology: SELAX are applied to low-power, high-speed circuits, and conventional ELC are used for the high- voltage circuits. The TFT degradation phenomena under dynamic stress are clarified, and the high-immunity TFT structure and high-quality gate insulator are proposed.
    ECS Transactions 10/2006; 3(8). DOI:10.1149/1.2356332
  • Y. Toyota · M. Matsumura · M. Hatano · T. Shiba · M. Ohkura
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    ABSTRACT: Pronounced device degradation and temperature dependence of p-channel polycrystalline silicon thin-film transistors (polysilicon TFTs) under pulse stress were investigated. This device degradation is due to the trap states produced by repetition between electron injection and hole injection. The analysis of activation energy affirms that the rapid degradation at high temperature is caused by an increase in the number of trapped holes, to which the negative-bias-temperature stress significantly contributes. The degradation is strongly dependent on the duration of hole injection and the location of the hole-injection region. To produce highly reliable TFT circuits, it is thus important to shorten the duration of hole injection and separate the region of hole injection from that of electron injection
    IEEE Transactions on Electron Devices 10/2006; DOI:10.1109/TED.2006.879680 · 2.36 Impact Factor
  • M. Matsumura · M. Hatano · T. Kaitoh · M. Ohkura
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    ABSTRACT: Trap-density analysis of laterally grown polysilicon films formed by continuous-wave laser revealed the main factor that controls the subthreshold property of low-temperature polysilicon thin-film transistors. In the low-current region, traps at the gate oxide/polysilicon interface are charged and the consequent insensitiveness of polysilicon surface potential to gate bias dominates the subthreshold property. In the higher current region, that is, close to the threshold voltage, a transport mechanism in which carriers are scattered at the grain boundaries becomes the dominant factor governing the subthreshold property.
    IEEE Electron Device Letters 05/2006; DOI:10.1109/LED.2006.871851 · 3.02 Impact Factor
  • Y. Toyota · M. Matsumura · M. Hatano · T. Shiba · T. Itoga · M. Ohkura
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    ABSTRACT: High-resolution (>300 ppi) system-in-displays have been developed by using mixed low-voltage/high-voltage poly-silicon TFTs. That is, ELC TFTs are used for the display circuits with high-voltage endurance, and SELAX TFTs are used for the low-power, high-performance display circuits. In this hybrid TFT, the SELAX TFTs successfully integrate reliability with high current drivability.
    SID Symposium Digest of Technical Papers 01/2005; 36(1). DOI:10.1889/1.2036278

Publication Stats

325 Citations
36.80 Total Impact Points


  • 2015
    • Tokyo Institute of Technology
      • Department of Physical Electronics
      Edo, Tōkyō, Japan
  • 2000–2012
    • Hitachi, Ltd.
      • Central Research Laboratory
      Edo, Tōkyō, Japan
  • 2002–2010
    • Daiwa House Central Research Laboratory
      Edo, Tōkyō, Japan
  • 1999–2002
    • University of California, Berkeley
      • Department of Mechanical Engineering
      Berkeley, CA, United States