[Show abstract][Hide abstract] ABSTRACT: A fully-integrated 16-element 60-GHz phased-array receiver is implemented in IBM 0.12-μm SiGe BiCMOS technology. The receiver employs RF-path phase-shifting and is designed for multi-Gb/s non-line of sight links in the 60-GHz ISM band (IEEE 802.15.3c and 802.11ad). Each RF front-end includes variable-gain LNAs and phase shifters with each front-end capable of 360° variable phase shift (11.25° phase resolution) from 57 GHz to 66 GHz with coarse/fine gain steps. A detailed analysis of the noise trade-offs in the receiver array design is presented to motivate architectural choices. The hybrid active and passive signal-combining network in the receiver uses a differential cross-coupled Gysel power combiner that reduces combiner loss and area. Each array front-end has 6.8-dB noise figure (at 22°C ) and the array has -10 dB to 58 dB programmable gain from single-input to output. Sixteen 60-GHz aperture-coupled patch-antennas and the RX IC are packaged together in multi-layer organic and LTCC packages. The packaged RX IC is capable of operating in all four IEEE 802.15.3c channels (58.32 to 64.8 GHz). Beam-forming and beam-steering measurements show good performance with 50-ns beam switching time. 5.3-Gb/s OFDM 16-QAM and 4.5 Gb/s SC 16-QAM links are demonstrated using the packaged RX ICs. Both line-of-sight links (~7.8 m spacing) and non-line-of-sight links using reflections (~9 m total path length) have been demonstrated with better than -18 dB EVM. The 16-element receiver consumes 1.8 W and occupies 37.7 mm<sup>2</sup> of die area.
[Show abstract][Hide abstract] ABSTRACT: This article summarizes the development of mature and highly integrated SiGe BiCMOS ICs for gigabit-per-second communications according to the requirements of the IEEE 802.15.3c and 802.11.ad-draft standards. A single-element transceiver chipset for point-to-point communications is described with emphasis on a feature-rich yet compact 60-GHz receiver. Next, a 16-element phased-array transceiver chipset for non-line-of-sight communications is described, with emphasis on a new power-efficient phased-array transmitter. Examples of gigabit-per-second line-of-sight and non-line-of-sight link experiments are provided, and system-level implementation trade-offs are discussed.
[Show abstract][Hide abstract] ABSTRACT: A phased-array transmitter (TX) for multi-Gb/s non-line-of-sight links in the four frequency channels of the IEEE 802.15.3c standard (58.32 to 64.8 GHz) is fully integrated in a 0.12-μm SiGe BiCMOS process. It consists of an up-conversion core followed by a 1:16 power distribution tree, 16 phase-shifting front-ends, and a digital control unit. The TX core is a two-step sliding-IF up-conversion chain with frequency synthesizer that features 40 dB of gain programmability, I/Q balance and LO leakage correction, and a modulator for 802.15.3c common-mode signaling. The tradeoffs involved in the implementation of a 1:16 power distribution network are analyzed and a hybrid passive/active distribution tree architecture is introduced. Each of the 16 front-ends consists of a balanced passive phase shifter and a variable-gain, 3-stage PA that features oP<sub>1dB</sub> programmability through the bias control of the its final stage. All of the chip features are digitally controllable and individual memory arrays are integrated at each front-end to enable fast beam steering through a high-speed parallel interface. The IC occupies 44 mm and is fully characterized on wafer. The TX delivers 9 to 13.5 dBm oPidB per element at 60.48 GHz with a total power consumption of 3.8 to 6.2 W. Each element attains a phase-shift range >360° with an amplitude variation <;±1 dB across phase settings and adjacent elements. Measurement results from a packaged IC in an antenna chamber are also presented including the demonstration of spatial power combining up to +40 dBm EIRP and 16-element radiation patterns.
[Show abstract][Hide abstract] ABSTRACT: This paper describes a single-chip, 70-80 GHz wireless transceiver utilizing a direct mm-wave QPSK modulator. The transceiver was fabricated in a 130 nm SiGe BiCMOS technology and can operate at data rates in excess of 18 Gb/s. The peak gain of the zero-IF receiver is 50 dB, the double sideband noise figure remains below 7 dB, while the 3-dB receive-chain bandwidth extends from DC to over 6 GHz. The differential transmitter achieves a maximum output power of +9 dBm. The total power consumption of the 1.9 mm × 1.1 mm transceiver is 1.2 W from 1.5, 2.5 and 3.3 V power supplies, including the 4 × 20-Gb/s PRBS generator.
[Show abstract][Hide abstract] ABSTRACT: A 0.12-μm SiGe phased-array Rx IC for beam-steered wireless communication in the 60-GHz band is described. It has 16 RF phase-shifting front-ends with 11° digital phase resolution and hybrid passive-active RF signal combining. It achieves 7.4-7.9 dB NF (not including 12-dB array gain) over the 4 IEEE channels. The IC has a double-conversion superheterodyne Rx core with a maximum of 72 dB of power gain in 1-dB steps, and the on-chip synthesizer achieves <; -90 dBc/Hz Rx phase noise at 1MHz offset. The IC draws 1.8 W at 2.7 V with a die area of 38 mm<sup>2</sup>. It has been packaged with 16 antennas in a 288-pin organic BGA and phased-array beamsteering has been demonstrated, along with 5+ Gb/s wireless links using 16-QAM OFDM.
Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE; 06/2010
[Show abstract][Hide abstract] ABSTRACT: A 60 GHz phased-array transmitter for multi-Gb/s non-line-of-sight links is fully integrated in a 0.12 Â¿m SiGe BiCMOS process. It consists of an up-conversion chain with synthesizer, a power distribution tree and 16 phase-shifting front-ends. The IC occupies 44 mm<sup>2</sup>, draws 1.2 W excluding front-ends, and delivers 9 to 13.5 dBm OP<sub>1dB</sub> per element drawing 164 to 313 mW per front-end.
[Show abstract][Hide abstract] ABSTRACT: This paper reviews recent research conducted at the University of Toronto on the development of CMOS transceivers aimed at operation in the 90-170-GHz range. Unique nanoscale CMOS issues related to millimeter-wave circuit design in the 65-nm node and beyond are addressed with an emphasis on transistor and top-level layout issues, low-voltage circuit topologies, and design flow. A Doppler transceiver and two receivers fabricated in a 65-nm GPLP CMOS technology are described, along with a single pole, double throw antenna switch with better than 5-dB insertion loss and 25-dB isolation in the entire 110-170-GHz band. The first receiver has an IQ architecture with a fundamental frequency voltage-controlled oscillator, and is intended for wideband passive imaging applications at 100 GHz. The measured noise figure and downconversion gain are 7-8 and 10.5 dB, respectively, while the 3-dB bandwidth extends from 85 to 100 GHz. The second receiver has double-sideband architecture, operates in the 135-145-GHz range (the highest for CMOS receivers), and features an 8-dB gain LNA, a double-balanced Gilbert cell mixer, and a dipole antenna. The 90-94-GHz Doppler transceiver, the highest frequency reported to date in CMOS, is intended for the remote monitoring of respiratory functions. A Doppler shift of 30 Hz, produced by a slow-moving (4.8 cm/s) target located at a distance of 1 m, was measured with a transmitter output power of approximately + 2 dBm and a phase noise of -90 dBc/Hz at 1 MHz offset. The range correlation effect is demonstrated for the first time in CMOS by measuring the phase noise of the received baseband signal at 10-Hz offset, clearly indicating that 1/ f noise has been canceled and it does not pose a problem in short-range applications, where neither a phase-locked loop nor a frequency divider are needed.
IEEE Transactions on Microwave Theory and Techniques 01/2010; 57(12)(12-57):3477 - 3490. DOI:10.1109/TMTT.2009.2034071 · 2.24 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This paper presents a complete 0.13 μm SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280 GHz f<sub>T</sub>/f<sub>MAX</sub>) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2 fF/μm<sup>2</sup> high-linearity MIM capacitor and complementary double gate oxide MOS transistors. Details are given on HBT integration, reliability and models as well as on back-end devices models.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a directly modulated, 60 GHz zero-IF transceiver architecture suitable for single-carrier, low-power, multi-gigabit wireless links in nanoscale CMOS technologies. This mm-wave front end architecture requires no upconversion of the baseband signals in the transmitter and no analog-to-digital conversion in the receiver, thus minimizing system complexity and power consumption. All circuit blocks are realized using sub-1.0 V topologies, that feature only a single high-frequency transistor between the supply and ground, and which are scalable to future 45 nm, 32 nm, and 22 nm CMOS nodes. The transceiver is fabricated in a 65 nm CMOS process with a digital back-end. It includes a receiver with 14.7 dB gain and 5.6 dB noise figure, a 60 GHz LO distribution tree, a 69 GHz static frequency divider, and a direct BPSK modulator operating over the 55-65 GHz band at data rates exceeding 6 Gb/s. With both the transmitter and the receiver turned on, the chip consumes 374 mW from 1.2 V which reduces to 232 mW for a 1.0 V supply. It occupies 1.28 times 0.81 mm<sup>2</sup>. The transceiver and its building blocks were characterized over temperature up to 85<sup>deg</sup> C and for power supplies down to 1 V. A manufacturability study of 60 GHz radio circuits is presented with measurements of transistors, the low-noise amplifier, and the receiver on slow, typical, and fast process splits. The transceiver architecture and performance were validated in a 1-6 Gb/s 2-meter wireless transmit-receive link over the 55-64 GHz range.
[Show abstract][Hide abstract] ABSTRACT: This paper reviews recent research conducted at the University of Toronto on the development of imaging and radio transceivers in CMOS, aimed at operation in the 100-GHz to 200-GHz range. Two receivers fabricated in 65-nm GPLP CMOS technology are described. The first is a 90-100 GHz IQ receiver with 7-dB noise figure, 10.5-dB downconversion gain and fundamental frequency VCO. The second receiver has a double-sideband architecture and operates in the 135-145 GHz range and features an 8-dB gain LNA, a double-balanced Gilbert cell mixer and a dipole antenna.
[Show abstract][Hide abstract] ABSTRACT: This paper describes a novel single-chip W-band wireless transceiver utilizing a direct mm-wave QPSK modulator. The transceiver was fabricated in a 130 nm SiGe BiCMOS technology and can operate at data rates in excess of 10 Gb/s. The Zero-IF receiver peak gain is 50 dB, the noise figure is 7 dB while the 3-dB IF bandwidth extends over 6 GHz. The differential transmitter achieves a maximum output power of +9 dBm, while the transceiver occupies 1.9 mm times 1.1 mm. The total power consumption, including the 4 times 20 Gb/s PRBS generator, is 1.2 W from 1.5, 2.5 and 3.3 V power supplies.
[Show abstract][Hide abstract] ABSTRACT: A four-stage 60 GHz low-noise amplifier is implemented in 65 nm CMOS with nMOS f<sub>t</sub> of 210 GHz. The LNA incorporates a reflection-type attenuator to provide variable gain with improved linearity in low-gain mode and a tunable notch filter for image rejection. The LNA, which consists of two common-source stages followed by two cascode stages, consumes 30.8 mW and achieves 5.9 dB NF and 15 dB gain at 60 GHz. The variable attenuator provides 10 dB of gain variation with the input-referred 1 dB compression point of the LNA being -15.1 dBm in high gain mode and -6 dBm in the low-gain mode. Each tunable notch filter stage provides an additional 8 dB attenuation of 37 GHz image signals, with the four-stage LNA achieving more than 35 dB image-rejection.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a complete 0.13 mum SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280GHz f<sub>T</sub>/f<sub>MAX</sub>) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2fF/mum<sup>2</sup> high-linearity MIM capacitor and complementary double gate oxide MOS transistors.
(Paper extended in IEEE JSSC journal : 0.13 m SiGe BiCMOS Technology Fully Dedicated to mm-Wave Applications)
Bipolar/BiCMOS Circuits and Technology Meeting, 2008. BCTM 2008. IEEE; 11/2008
[Show abstract][Hide abstract] ABSTRACT: This paper presents the first single-chip direct-conversion 77-85 GHz transceiver fabricated in SiGe HBT technology, intended for Doppler radar and millimeter-wave imaging, particularly within the automotive radar band of 77-81 GHz. A 1.3 mm times 0.9 mm 86-96 GHz receiver is also presented. The transceiver, fabricated in a 130 nm SiGe HBT technology with f<sub>T</sub>/f<sub>MAX</sub> of 230/300 GHz, consumes 780 mW, and occupies 1.3 mm times 0.9 mm of die area. Furthermore, it achieves 40 dB conversion gain in the receiver at 82 GHz, a 3 dB bandwidth extending from 77 to 85 GHz at 25degC, and covering the entire 77-81 GHz band up to 100degC, record 3.85 dB DSB noise figure measured at 82 GHz LO and 1 GHz IF, and an IP<sub>1dB</sub> of -35 dBm. The transmitter provides + 11.5 dBm of saturated output power at 77 GHz, and a divide64 static frequency divider is included on-die. Successful detection of a Doppler shift of 30 Hz at a range of 6 m is shown. The 86-96 GHz receiver achieves 31 dB conversion gain, a 3 dB bandwidth of 10 GHz, and 5.2 dB DSB noise figure at 96 GHz LO and 1 GHz IF, and -99 dBc/Hz phase noise at 1 MHz offset. System-level layout and integration techniques that address the challenges of low-voltage transceiver implementation are also discussed.
[Show abstract][Hide abstract] ABSTRACT: This work summarizes upcoming millimeter wave and high speed applications which will benefit from advanced SiGe BiCMOS process. The performance of a 230 GHz f<sub>T</sub> 280 GHz f<sub>max</sub> process is detailed and future improvements are discussed. Intrinsic transistor performance for millimeter wave design has been compared with that of advanced 65 nm Low-Power CMOS. To help process comparison, design examples are also given and circuit optimizations to reach optimum noise figure are discussed. Recent realizations at 24 GHz and 77 GHz in SiGe BiCMOS are presented, demonstrating state of the art results on both receivers.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a 1.2 V 60 GHz zero-IF transceiver fabricated in a 65 nm CMOS process with a digital back-end. The chip includes a receiver with 14.7 dB gain, a low 5.6 dB noise figure, a 60 GHz LO distribution tree, a 64 GHz static frequency divider, and a direct BPSK modulator operating over the 55-65 GHz band at data rates exceeding 3.5 Gb/s. The chip consumes 374 mW (232 mW) from 1.2 V (1.0 V) and occupies 1.28 times 0.81 mm<sup>2</sup>. The transceiver was characterized over temperature up to 85degC and for power supplies down to 1 V. A manufacturability study of 60 GHz radio circuits is presented with measurements of transistors, the low-noise amplifier, and the receiver on typical and fast process splits. The transceiver performance is demonstrated using a 3.5 Gb/s 2-meter wireless transmit-receive link over the 55-64 GHz range.
[Show abstract][Hide abstract] ABSTRACT: In this paper we review a bit more than 10 years of SiGe BiCMOS technology development and present the best results published to date by the main contenders in the field. Next, with the support of recent results obtained at STMicroelectronics, we discuss the process optimization that led to further increase in the device operating speed. Finally, we present the characteristics of a 260GHz f<sub>T</sub>, 340GHz f<sub>max</sub> SiGe HBT technology along with recent circuit results demonstrated in this technology.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a complete 2.5-V 77-GHz chipset for Doppler radar and imaging applications fabricated in SiGe HBT and SiGe BiCMOS technologies. The chipset includes a 123-mW single-chip receiver with 24-dB gain and an IP<sub>1</sub> <sub>dB</sub> of -21.7 dBm at 76-GHz local oscillator (LO) and 77-GHz RF, 4.8-dB double-sideband noise figure at 76-GHz LO and 1-GHz IF, and worst case -98.5 dBc/Hz phase noise at 1-MHz offset over the entire voltage-controlled oscillator tuning range at room temperature. Monolithic spiral inductors and transformers result in a receiver core area of 450 mum times 280 mum. For integration of an entire 77-GHz transceiver, a power amplifier with 19-dB gain, +14.5-dBm saturated output power, and 15.7% power-added efficiency is demonstrated. Frequency divider topologies for 2.5-V operation are investigated and measurement results show a 105-GHz static frequency divider consuming 75 mW, and a 107-GHz Miller divider consuming 33 mW. Measurements on all circuits confirm operation up to 100 <sup>deg</sup> C. Low-power low-noise design techniques for each circuit block are discussed.
IEEE Transactions on Microwave Theory and Techniques 06/2008; 56(5-56):1092 - 1104. DOI:10.1109/TMTT.2008.921268 · 2.24 Impact Factor