[Show abstract][Hide abstract] ABSTRACT: The recently introduced Vertical Slit Field Effect Transistor allows for adjusting its threshold voltage through independent controllable gates. This feature can be applied to a broad range of circuits. In this paper two examples are presented. First, a ring oscillator with a wide frequency tuning range and second, a Schmitt trigger with a controllable hysteresis.
[Show abstract][Hide abstract] ABSTRACT: Circuits with transistors using independently controlled gates have been proposed to reduce the number of transistors and to increase the logic density per area. So far only small building blocks have been presented. This paper investigates for the first time the use of independent double gate transistors in 16 bit ripple carry and parallel prefix adders. New adder circuits and the trade-off between area reduction, delay and power consumption are presented. Area and transistor count reduction by one third can be achieved.
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on; 06/2009
[Show abstract][Hide abstract] ABSTRACT: A stacked three-dimensional six transistor SRAM cell using a novel vertical slit field effect transistor with two independently controlled gates is proposed. A compact stacked 3D memory cell topology with a highly regular layout is presented and a significant memory cell area reduction can be achieved. Utilization of independent double gate transistors enhances the robustness for read and write operation. The trade-off for the use of independently controlled gates to increase the cell stability is discussed.
IC Design and Technology, 2009. ICICDT '09. IEEE International Conference on; 06/2009
[Show abstract][Hide abstract] ABSTRACT: Circuits with transistors using independently controlled gates have been proposed to reduce the number of transistors and to increase the logic density per area. This paper introduces a novel Vertical Slit Field Effect Transistor with unique independent double gate properties to demonstrate the possible advantages for independent double gate circuits. A new adder circuit is proposed, where the power could be reduced by one fifth and the area by on third compared to a tied gate configuration.
[Show abstract][Hide abstract] ABSTRACT: We present fabrication, optimization and application aspects of complementary Multiple-Gate Tunneling FETs (MuGTFETs). Tunneling FETs are implemented in a MuGFET technology for the first time. N- and p-type tunneling currents are observed within a single device structure. Digital and analog device performance is analyzed. Measured devices show low on currents in the tens of nA regime due to not optimized doping profiles. However, promising analog characteristics are obtained with intrinsic gain of more than 300 for 65 nm channel length devices. The scaling potential of multi-gate tunneling FETs is proven by measurements and device simulations that reveal a low dependence of the device characteristics on the channel length. The devices feature low temperature dependence and competitive matching behavior. A new voltage reference circuit is proposed as potential application for the MuGTFET.
[Show abstract][Hide abstract] ABSTRACT: Previously published results by the authors, from 2004 to 2006, on the tunneling field-effect transistor (TFET) are revised in this correction. The devices that they had characterized as TFETs contain a conducting path in parallel to the intended tunneling junction. Therefore, the measured characteristics are similar to a MOSFET with a resistive source connection
IEEE Electron Device Letters 05/2007; · 2.79 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.