[show abstract][hide abstract] ABSTRACT: The interest on emerging nanotechnologies has been
recently focused on NanoMagnetic Logic (NML), which has
unique appealing features. NML circuits have a very low power
consumption and, due to their magnetic nature, they maintain the
information safely stored even without power supply. The nature
of these circuits is highly different from the CMOS one. As a
consequence, to better understand NML logic, complex circuits
and not only simple gates must be designed. This constraint calls
for a new design and simulation methodology. It should efficiently
encompass manifold properties: 1) being based on commonly
used hardware description language (HDL) in order to easily
manage complexity and hierarchy; 2) maintaining a clear link
with physical characteristics 3) modeling performance aspects
like speed and power, together with logic behavior.
In this contribution we present a VHDL behavioral model for
NML circuits, which allows to evaluate not only logic behavior
but also power dissipation. It is based on a technological solution
called “snake-clock”. We demonstrate this model on a case study
which offers the right variety of internal substructures to test the
method: a four bit microprocessor designed using asynchronous
logic. The model enables a hierarchical bottom-up evaluation of
the processor logic behavior, area and power dissipation, which
we evaluated using as benchmark a division algorithm. Results
highlight the flexibility and the efficiency of this model, and the
remarkable improvements that it brings to the analysis of NML
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 08/2013; 1410-1420:21-8. · 1.22 Impact Factor
[show abstract][hide abstract] ABSTRACT: In the last decade Quantum dot Cellular Automata technology has been one of the most studied among the emerging technologies. The magnetic implementation, NanoMagnet Logic (NML), is particularly interesting as an alternative solutions to CMOS technology. The main advantages of NML circuits resides in the possibility to mix logic and memory in the same device, the expected low power consumption and the remarkable tolerance to heat and radiations. NML and QCA circuits behavior is different w.r.t. their CMOS counterparts. Consequently architecture organization must be tailored to their characteristics, and it is important to identify which applications are best suited for this technology. Our contribution reported in this paper represents a considerable step-forward in this direction. We present an optimized implementation on NML technology of an hardware accelerator for biosequences analysis. The architecture leverages the systolic array structure, which is the best organization for this technology due to the regularity of the layout. The circuit is described using a VHDL model, simulated to verify the correct functionality from the application point of view, and performance are evaluated, both in terms of speed and power consumption. Results pinpoints that NML technology with the appropriate clock solution can reach a considerable reduction in power consumption over CMOS. This analysis highlights quantitatively, and not only qualitatively, that NML logic is perfectly suited for Massively Parallel Data Analysis applications
International Conference on IC Design and Technology; 01/2013
[show abstract][hide abstract] ABSTRACT: A common element in emerging nanotechnologies is the increasing complex- ity of the problems to face when attempting the design phase, because issues related to technology, specific application and architecture must be evalu- ated simultaneously. In several cases faced problems are known, but require a fresh re-think on the basis of different constraints not enforced by standard design tools. Among the emerging nanotechnologies, the two-dimensional structures based on nanowire arrays is promising in particular for massively parallel architec- tures. Several studies have been proposed on the exploration of the space of architectural solutions, but only a few derived high-level information from the results of an extended and reliable characterization of low-level structures. The tool we present is of aid in the design of circuits based on nanotech- nologies, here discussed in the specific case of nanowire arrays, as best candi- date for massively parallel architectures. It enables the designer to start from a standard High-level Description Languages (HDL), inherits constraints at physical level and applies them when organizing the physical implementation of the circuit elements and of their connections. It provides a complete simu- lation environment with two levels of refinement. One for DC analysis using a fast engine based on a simple switch level model. The other for obtaining transient performance based on automatic extraction of circuit parasitics, on detailed device (nanowire-FET) information derived by experiments or by existing accurate models, and on spice-level modeling of the nanoarray. Re- sults about the method used for the design and simulation of circuits based on nanowire-FET and nanoarray will be presented
Journal of Parallel and Distributed Computing 01/2013;
[show abstract][hide abstract] ABSTRACT: Quantum dot Cellular Automata (QCA) is an emerg-
ing nanotechnology that has gained significant research interest
in recent years. Extremely small feature sizes, ultra low power
consumption and high clock frequency make QCA a potentially
attractive solution for implementing computing architectures at
the nano-scale. To be considered as a suitable CMOS substitute,
the QCA technology must be able to implement complex real
time applications with affordable complexity. Low Density Parity
Check (LDPC) decoding is one of such applications. The core of
LDPC decoding lies in the check node (CN) processing element
which executes actual decoding algorithm and contributes to-
wards overall performance and complexity of LDPC decoder.
This work presents a novel QCA architecture for partial
parallel, layered LDPC check node. The check node executes
Normalized Min Sum decoding algorithm and is flexible to
support check node degree dc up to 20. The check node is
constructed using a VHDL behavioral model of QCA elementary
circuits which provides a hierarchical bottom up approach to
evaluate the logical behavior, area and power dissipation of whole
design. Performance evaluations are reported for the two main
implementations of QCA i.e. molecular and magnetic.
IEEE Transactions on Nanotechnology 01/2013; PP(99):1-1. · 1.80 Impact Factor
[show abstract][hide abstract] ABSTRACT: The recently proposed NanoMagnet based Logic (NML) represents an innovative
way to assemble electronic logic circuits.
The low power consumption, combined with the possibility to maintain the
information stored without power supply, allows to design low power
digital circuits far beyond the limitations of CMOS technology.
This work is focused on the key logic block of NanoMagnet
based Logic, the Majority Voter (MV). It is
thoroughly analyzed through detailed micromagnetic simulations,
changing the geometrical parameters,
and detecting logic behavior, timing performance and energy dissipation.
Our analysis enables to derive important results,
enhancing the practical knowledge of NML.
First, we demonstrate that NML circuits can be effectively
fabricated not only using
Electron Beam Lithography, but also using high-end optical lithography
without loosing performance.
This is a promising opportunity for the future of this technology.
Second, we demonstrate the robustness of the MV
considering process variations and extracting useful guidelines
for its technological implementation.
Third, we show how, and how much, the alteration of magnets
sizes and distances affect
timing and energy consumption. Finally, fourth, we outline
the problematic fabrication of the gate with real clock wires,
and propose a modification that enables
the fabrication of working gates, remarkably enhancing the
possibilities of this technology.
IEEE Transactions on Nanotechnology 01/2012; 11(5):940-947. · 1.80 Impact Factor
[show abstract][hide abstract] ABSTRACT: Ultra Deep Sub-Micron (UDSM) processes, as well as beyond CMOS technology choices, influence circuits performance with a chain of consequences through devices, circuits and systems that are difficult to predict. Nonetheless effective design-space exploration enables process optimization and early design organization. We introduce TAMTAMS, a tool based on an open, flexible and simple structure, which allows to predict system level features starting from technology variables. It is modular and based on a clear dependency tree of modules, each related to a model of specific quantities (e.g. device currents, circuit delay, interconnects noise, ….) presented in literature. Models can be compared and sensitivity to parameters observed. We believe our contribution gives a fresh point of view on process-to-system predictors. Though still in development, it already shows flexibility and allows a traceable path of a technology parameter on its way to the system level.
Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on; 01/2012
[show abstract][hide abstract] ABSTRACT: Biosequence alignment recently received an amazing
support from both commodity and dedicated hardware plat-
forms. The limitless requirements of this application motivate
the search for improved implementations to boost processing
time and capabilities. We propose an unprecedented hardware
improvement to the classic Smith-Waterman (S-W) algorithm
based on a twofold approach: i) an on-the-fly gap-open/gap-
extension selection that reduces the hardware implementation
complexity; ii) a pre-selection filter that uses reduced amino-acid
alphabets to screen out not-significant sequences and to shorten
the S-W iterations on huge reference databases. We demonstrated
the improvements w.r.t. a classic approach both from the point
of view of algorithm efficiency and of HW performance (FPGA
and ASIC post-synthesis analysis).
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on; 01/2012
[show abstract][hide abstract] ABSTRACT: Emerging computing technologies inherently exhibit high process and timing variation. Many researchers believe that an asynchronous approach is likely to play an enabling role in making these technologies feasible. This article compares the cost and performance of fully synchronous and mixed synchronous asynchronous implementations of quantum cellular automata, and makes the case that asynchrony is inevitable at the top levels of QCA designs.
IEEE Design and Test of Computers 11/2011; · 1.62 Impact Factor
[show abstract][hide abstract] ABSTRACT: The International Technology Roadmap of semiconductors suggests that quantum-dot cellular automata (QCA) technology might be a possible CMOS substitute. In particular, magnetic quantum-dot cellular automata (MQCA) have recently drawn the attention of the researchers. Previous experimental works have demonstrated that MQCA are feasible, and can be fabricated with existing technological processes. They are also attractive due to their compactness and an extremely small power dissipation. Unlike in previous contributions, where architectural blocks are often presented without or only slightly considering their relations with technology, here we conceived, implemented, and described a complex MQCA computational block maintaining a clear link with technology. This link is achieved at different levels. At an architectural level, we propose the use of delay insensitive null convention logic (NCL) . It is implemented for MQCA in order to solve the “layout=timing” problem in the specific case of MQCA. We, thus, describe an architectural block at system level using a hardware description language (HDL). This NCL-HDL idea is adapted to a new structure, which we have called “snake clock,” proposed as a feasible solution for the problem of clock delivery, essential for MQCA operations. Furthermore, we demonstrated by means of accurate micromagnetic and finite element method simulations that the three-phase “snake-clock” NCL structure works correctly.
IEEE Transactions on Nanotechnology 10/2011; · 1.80 Impact Factor
[show abstract][hide abstract] ABSTRACT: New solutions are required to overcome the limitations of scaled CMOS technology in the years to come.
One proposed approach consists in adopting Nano-Magnetic Logic Circuits, highly appealing for their extremely
reduced power consumption. Despite its interesting nature, many problems arise when this technology is considered
for realistic designs. Among these, the most critical from the circuit implementation point of view is the wire, which
works as a pipelined interconnect, and which delay in terms of clock cycles depends on its length. Remarkable
constraints arise at the design phase, both in terms of synthesis and of physical design.
One possible solution to this problem is the use of a delay insensitive asynchronous logic, the Null Convention
Logic (NCLT M ). Nevertheless its use has many negative consequences in terms of area occupation and speed loss
with respect to a Boolean version. In this paper we analyze and compare different solutions: nanomagnetic circuits
based on full NCL, mixed Boolean-NCL and fully Boolean logic. We discuss the advantages of these logics but
also the issues they arise. In particular we analyze feedback signals, which, due to their intrinsic pipelined nature,
cause errors that still have not found a solution in the literature. The innovative arrangement we propose solves
most of the problems and thus soundly increases the knowledge on this technology. The analysis is performed
using a VHDL behavioral model that we developed and a microprocessor we designed, based on this model, as a
sound and realistic test bench.
[show abstract][hide abstract] ABSTRACT: Among the "beyond CMOS" alternatives, Quantum dot Cellular Automata represents an innovative way to imple- ment digital circuits. Particularly, the magnetic implementation (MQCA) favours the fabrication of circuits with a tiny power dissipation and with intrinsic memory capability. In this contribution we deeply analyse the key logic gate of MQCA circuits, the Majority Voter (MV), taking into account its physical feasibility and its consequent expected performance. Detailed simulations of the majority voter using a low level micromagnetic simulator, are reported. We have changed the distance among nanomagnets and their aspect ratio, to represent process variations. We have verified the range of operations of the gate and we have also performed a timing analysis. Results show how the delay of the gate changes if the distance between neighbour magnets is varied, demonstrating that the choice of the distance must be carefully done in order to balance the physical feasibility and the gate delay.