[Show abstract][Hide abstract] ABSTRACT: Among emerging technologies Quantum dot Cellular Automata (QCA) plays a fundamental role. Its magnetic version, normally called NanoMagnet Logic (NML), is particularly interesting thanks to the ability to work at room temperature and to mix logic and memory in the same device. Magnetic circuits have also a potential very low power consumption. Unfortunately classic NML circuits are normally driven (clocked) with a current generating a clocked magnetic field, nullifying the possibility to actually obtain low power circuits. We have recently developed a technology-friendly solution, the MagnetoElastic NML (ME-NML), where magnetic circuits are driven through an electric field, and not with a current, drastically reducing the power consumption. In this paper we start to explore the architectural consequences of this new magnetic technology. The analysis is performed using as a benchmark a Galois multiplier, a systolic architecture particularly suited for QCA and NML technologies. The layout is precisely described and the resulting circuit is modeled and simulated using VHDL language. The obtained results are remarkable. The circuit area is reduced by 4 times compared to classic NML approach. This, coupled with the intrinsic lower power consumption due to different clock, leads to a 50 times reduction of power absorption. Moreover the particular structure of magnetoelastic NML allows to define a library of standard cells that can be easily used by designers and automatic layout tools to design circuits, greatly improving future research in this field.
Nanoscale Architectures (NANOARCH), 2014 IEEE/ACM International Symposium on; 07/2014
[Show abstract][Hide abstract] ABSTRACT: In recent years magnetic-based technologies, like NanoMagnet Logic (NML), are gaining increasing interest as possible substitutes of CMOS transistors. The possibility to mix logic and memory in the same device, coupled with a potential low power consumption, opens up completely new ways of developing circuits. The major issue of this technology is the necessity to use an external magnetic field as clock signal to drive the
information through the circuit. The power losses due to the magnetic field generation potentially wipe out any advantages of NML logic. To solve the problem new clock mechanisms were developed, based on spin-transfer torque current and on voltage-controlled multiferroic structures that use magnetoelastic properties of magnetic materials, i.e. exploiting the possibility of influencing magnetization dynamics by means of the elastic tensor. In particular the latter shows an extremely low power consumption.
In this paper we propose an innovative voltage-controlled magnetoelastic clock system aware of the technological constraints risen by modern fabrication processes. We show how circuits can be fabricated taking into account technological limitations and we evaluate the performance of the proposed system. Results show that the proposed solution promises remarkable improvements over other NML approaches, even though state-of-the-art ideal multiferroic logic has in theory better performance. Moreover, since the proposed approach is technology-friendly, it gives a substantial contribution toward the fabrication of a full magnetic circuit and represents an optimal trade off between performance and feasibility.
IEEE Transactions on Nanotechnology 07/2014; · 1.80 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Among Field-Coupled technologies, NanoMagnet Logic (NML) is one of the most promising. Low dynamic power consumption, total absence of static power, remarkable heat and radiations resistance, in association with the possibility of combining memory and logic in the same device, make this technology the ideal candidate for low power, portable applications. However, the necessity of using an external magnetic field to locally control the circuit represents, currently, the weakest point of this technology. The high power losses in the clock generation system adopted up to now wipes out the most important advantages of this technology.
In this chapter we discuss a clock system based on a piezoelectric actuator that allows electrical control of NanoMagnet Logic circuits. The low power consumption coupled with the fact that electric fields are easier to generate at the nanoscale level makes this clock system a strong candidate as the final and effective clocking mechanism for this technology. Another remarkable advantage of the proposed solution resides in its compatibility with currently available technology.
Field-Coupled Nanocomputing, Paradigms, Progress, and Perspectives, Edited by Neal G. Anderson firstname.lastname@example.org (15) Sanjukta Bhanja email@example.com, 01/2014: pages 73-110; Springer Berlin Heidelberg., ISBN: 978-3-662-43722-3
[Show abstract][Hide abstract] ABSTRACT: The interest on emerging nanotechnologies has been
recently focused on NanoMagnetic Logic (NML), which has
unique appealing features. NML circuits have a very low power
consumption and, due to their magnetic nature, they maintain the
information safely stored even without power supply. The nature
of these circuits is highly different from the CMOS one. As a
consequence, to better understand NML logic, complex circuits
and not only simple gates must be designed. This constraint calls
for a new design and simulation methodology. It should efficiently
encompass manifold properties: 1) being based on commonly
used hardware description language (HDL) in order to easily
manage complexity and hierarchy; 2) maintaining a clear link
with physical characteristics 3) modeling performance aspects
like speed and power, together with logic behavior.
In this contribution we present a VHDL behavioral model for
NML circuits, which allows to evaluate not only logic behavior
but also power dissipation. It is based on a technological solution
called “snake-clock”. We demonstrate this model on a case study
which offers the right variety of internal substructures to test the
method: a four bit microprocessor designed using asynchronous
logic. The model enables a hierarchical bottom-up evaluation of
the processor logic behavior, area and power dissipation, which
we evaluated using as benchmark a division algorithm. Results
highlight the flexibility and the efficiency of this model, and the
remarkable improvements that it brings to the analysis of NML
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 08/2013; 1410-1420:21-8. · 1.22 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: In the last decade Quantum dot Cellular Automata technology has been one of the most studied among the emerging technologies. The magnetic implementation, NanoMagnet Logic (NML), is particularly interesting as an alternative solutions to CMOS technology. The main advantages of NML circuits resides in the possibility to mix logic and memory in the same device, the expected low power consumption and the remarkable tolerance to heat and radiations. NML and QCA circuits behavior is different w.r.t. their CMOS counterparts. Consequently architecture organization must be tailored to their characteristics, and it is important to identify which applications are best suited for this technology. Our contribution reported in this paper represents a considerable step-forward in this direction. We present an optimized implementation on NML technology of an hardware accelerator for biosequences analysis. The architecture leverages the systolic array structure, which is the best organization for this technology due to the regularity of the layout. The circuit is described using a VHDL model, simulated to verify the correct functionality from the application point of view, and performance are evaluated, both in terms of speed and power consumption. Results pinpoints that NML technology with the appropriate clock solution can reach a considerable reduction in power consumption over CMOS. This analysis highlights quantitatively, and not only qualitatively, that NML logic is perfectly suited for Massively Parallel Data Analysis applications
International Conference on IC Design and Technology; 01/2013
[Show abstract][Hide abstract] ABSTRACT: Quantum dot Cellular Automata (QCA) is an emerg-
ing nanotechnology that has gained significant research interest
in recent years. Extremely small feature sizes, ultra low power
consumption and high clock frequency make QCA a potentially
attractive solution for implementing computing architectures at
the nano-scale. To be considered as a suitable CMOS substitute,
the QCA technology must be able to implement complex real
time applications with affordable complexity. Low Density Parity
Check (LDPC) decoding is one of such applications. The core of
LDPC decoding lies in the check node (CN) processing element
which executes actual decoding algorithm and contributes to-
wards overall performance and complexity of LDPC decoder.
This work presents a novel QCA architecture for partial
parallel, layered LDPC check node. The check node executes
Normalized Min Sum decoding algorithm and is flexible to
support check node degree dc up to 20. The check node is
constructed using a VHDL behavioral model of QCA elementary
circuits which provides a hierarchical bottom up approach to
evaluate the logical behavior, area and power dissipation of whole
design. Performance evaluations are reported for the two main
implementations of QCA i.e. molecular and magnetic.
IEEE Transactions on Nanotechnology 01/2013; PP(99):1-1. · 1.80 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: A common element in emerging nanotechnologies is the increasing complex- ity of the problems to face when attempting the design phase, because issues related to technology, specific application and architecture must be evalu- ated simultaneously. In several cases faced problems are known, but require a fresh re-think on the basis of different constraints not enforced by standard design tools. Among the emerging nanotechnologies, the two-dimensional structures based on nanowire arrays is promising in particular for massively parallel architec- tures. Several studies have been proposed on the exploration of the space of architectural solutions, but only a few derived high-level information from the results of an extended and reliable characterization of low-level structures. The tool we present is of aid in the design of circuits based on nanotech- nologies, here discussed in the specific case of nanowire arrays, as best candi- date for massively parallel architectures. It enables the designer to start from a standard High-level Description Languages (HDL), inherits constraints at physical level and applies them when organizing the physical implementation of the circuit elements and of their connections. It provides a complete simu- lation environment with two levels of refinement. One for DC analysis using a fast engine based on a simple switch level model. The other for obtaining transient performance based on automatic extraction of circuit parasitics, on detailed device (nanowire-FET) information derived by experiments or by existing accurate models, and on spice-level modeling of the nanoarray. Re- sults about the method used for the design and simulation of circuits based on nanowire-FET and nanoarray will be presented
Journal of Parallel and Distributed Computing 01/2013; · 1.12 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Among renewable energy sources, wind is one of the most exploited, due to the relative low cost and independence from the sun. However, to harvest the highest amount of energy, it is important to maximize the global efficiency of the wind generator. To do so it is necessary to understand the behavior of each mechanical and electrical component and specifically how they interact. In this work we present WindDesigner, an open tool for wind generators analysis and design. It allows to dynamically configure the composition of the generator and to estimate important parameters, like efficiency and energy production, according to the variation of wind speed. It is written in Matlab and its modular and open structure can be easily expanded and improved. The tool has been applied to the design of a specific wind generator, enabling design space exploration and selection of alternative implementation options. Thanks to WindDesigner it will be possible to design the optimum wind generator structure for every site condition and load needs.
Clean Electrical Power (ICCEP), 2013 International Conference on; 01/2013
[Show abstract][Hide abstract] ABSTRACT: In order to assure the best learning experience, the teaching activity in Electronic Engineering is expected to closely follow the rapid evolution of CMOS technology. As a consequence the necessity of new teaching tools arises. These instruments must be flexible enough not only to follow technology evolution, but also to improve the learning experience by assuring interactivity and adaptability. In this work we present a tool “made by students for other students” which analyzes and compares different technologies from nanoscale CMOS transistors to emerging technologies, based for example on Carbon Nanotubes and Silicon Nanowires. The aim of this tool is to grant the students, but also the designers, with a useful instrument to understand the impact of scaling and of emerging technologies on nanoelectronics circuits. It allows the evaluation of different circuit parameters, from device level (currents, capacitances, ...) to system level (power, speed, area, ...). Since the best way to learn is “learning by doing”, the tool, based on the open source software GNU Octave, has a modular structure. In this way students not only can use it, but they can develop new modules starting from the literature, from teacher's experiences or from interesting case studies, contributing themselves to improve the learning experience of other students.
[Show abstract][Hide abstract] ABSTRACT: The recently proposed NanoMagnet based Logic (NML) represents an innovative
way to assemble electronic logic circuits.
The low power consumption, combined with the possibility to maintain the
information stored without power supply, allows to design low power
digital circuits far beyond the limitations of CMOS technology.
This work is focused on the key logic block of NanoMagnet
based Logic, the Majority Voter (MV). It is
thoroughly analyzed through detailed micromagnetic simulations,
changing the geometrical parameters,
and detecting logic behavior, timing performance and energy dissipation.
Our analysis enables to derive important results,
enhancing the practical knowledge of NML.
First, we demonstrate that NML circuits can be effectively
fabricated not only using
Electron Beam Lithography, but also using high-end optical lithography
without loosing performance.
This is a promising opportunity for the future of this technology.
Second, we demonstrate the robustness of the MV
considering process variations and extracting useful guidelines
for its technological implementation.
Third, we show how, and how much, the alteration of magnets
sizes and distances affect
timing and energy consumption. Finally, fourth, we outline
the problematic fabrication of the gate with real clock wires,
and propose a modification that enables
the fabrication of working gates, remarkably enhancing the
possibilities of this technology.
IEEE Transactions on Nanotechnology 01/2012; 11(5):940-947. · 1.80 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Biosequence alignment recently received an amazing
support from both commodity and dedicated hardware plat-
forms. The limitless requirements of this application motivate
the search for improved implementations to boost processing
time and capabilities. We propose an unprecedented hardware
improvement to the classic Smith-Waterman (S-W) algorithm
based on a twofold approach: i) an on-the-fly gap-open/gap-
extension selection that reduces the hardware implementation
complexity; ii) a pre-selection filter that uses reduced amino-acid
alphabets to screen out not-significant sequences and to shorten
the S-W iterations on huge reference databases. We demonstrated
the improvements w.r.t. a classic approach both from the point
of view of algorithm efficiency and of HW performance (FPGA
and ASIC post-synthesis analysis).
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on; 01/2012
[Show abstract][Hide abstract] ABSTRACT: Quantum dot Cellular Automata (QCA) is an emerging nanotechnology paradigm that is currently being investigated as a possible CMOS substitute. It offers higher speed and lower area and power consumption than CMOS transistors. However, due to its intrinsic pipelined nature, QCA circuits suffer from serious throughput reductions due to feedback signals. As a consequence to fully exploit the true potential of this technology, circuits architecture must be designed with the aim to reduce or eliminate the presence of feedbacks. This work proposes as a relevant design case, the QCA implementation of Fast Fourier Transform (FFT) Algorithm. A novel architecture for partial parallel FFT processor is presented which not only reduces the circuit complexity but also eliminates the need of feedback signals, allowing to maximize the throughput. The proposed architecture is described using an accurate, layout aware VHDL model which is exploited in a hierarchical bottom up approach to evaluate the logical behavior, area and power dissipation of whole design. This innovative approach widely expands the field of application for QCA circuits.
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on; 01/2012
[Show abstract][Hide abstract] ABSTRACT: Ultra Deep Sub-Micron (UDSM) processes, as well as beyond CMOS technology choices, influence circuits performance with a chain of consequences through devices, circuits and systems that are difficult to predict. Nonetheless effective design-space exploration enables process optimization and early design organization. We introduce TAMTAMS, a tool based on an open, flexible and simple structure, which allows to predict system level features starting from technology variables. It is modular and based on a clear dependency tree of modules, each related to a model of specific quantities (e.g. device currents, circuit delay, interconnects noise, ….) presented in literature. Models can be compared and sensitivity to parameters observed. We believe our contribution gives a fresh point of view on process-to-system predictors. Though still in development, it already shows flexibility and allows a traceable path of a technology parameter on its way to the system level.
Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on; 01/2012