W. Hafez

Publications (6)0 Total impact

• Conference Proceeding: A 32nm low power RF CMOS SOC technology featuring high-k/metal gate

  P. VanDerVoorn, M. Agostinelli, S. Choi, G. Curello, H. Deshpande, M.A. El-Tanani, W. Hafez, U. Jalan, L. Janbay, M. Kang, [......], S. Taylor, C. Tsai, H. Xu, J. Xu, L. Yang, I. Young, J. Yeh, J. Yip, P. Bai, C. Jan
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  ABSTRACT: A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices with high performance and very low leakage to address advanced RF/mobile communications markets. A high performance NMOS achieves an f_T of 420GHz. Concurrently, a low leakage 30pA/um NMOS achieves an f_T of 218GHz. Deep-nwell/guard rings improves noise isolation by >50dB. High Q inductors, >7V breakdown voltage power amplifier transistors, varactors, and precision passives are also presented.
  VLSI Technology (VLSIT), 2010 Symposium on; 07/2010
• Conference Proceeding: Reliability studies on a 45nm low power system-on-chip (SoC) dual gate oxide high-k / metal gate (DG HK+MG) technology

  C. Prasad, P. Bai, S. Gannavaram, W. Hafez, J. Hicks, C. Jan, J. Lin, M. Jones, K. Komeyli, R. Kotlyar, K. Mistry, I. Post, C. Tsai
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  ABSTRACT: In this paper, we present extensive reliability characterization results for a novel dual gate 45 nm HK+MG technology. BTI, HCI and TDDB degradation modes on the Logic and I/O transistors are studied and excellent reliability is demonstrated. Emphasis is placed on the importance of process optimizations to support robust I/O transistors while maintaining the high performance and reliability of Logic transistors. Monitoring of reliability for HVM and collateral reliability are also addressed.
  Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
• Source

  Available from: intel.com

  Conference Proceeding: A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

  C.-H. Jan, M. Agostinelli, M. Buehler, Z.-P. Chen, S.-J. Choi, G. Curello, H. Deshpande, S. Gannavaram, W. Hafez, U. Jalan, [......], H. Tashiro, C. Tsai, P. Vandervoorn, J. Xu, L. Yang, J.-Y. Yeh, J. Yip, K. Zhang, Y. Zhang, P. Bai
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  ABSTRACT: A leading edge 32 nm high-k/metal gate transistor technology has been optimized for SoC platform applications that span a wide range of power, performance, and feature space. This technology has been developed to be modular, offering mix-and-match transistors, interconnects, RF/analog passive elements, embedded memory, and noise mitigation options. The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently. Embedded memories include high density (0.148 um²) and low voltage (0.171 um²) SRAMs as well as secure OTP fuses. Analog/RF SoC features include high precision, high quality passives (resistors, capacitors and inductors) and deep-nwell noise isolation.
  Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
• Conference Proceeding: A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

  C.-H. Jan, P. Bai, S. Biswas, M. Buehler, Z.-P. Chen, G. Curello, S. Gannavaram, W. Hafez, J. He, J. Hicks, [......], J. Rizk, G. Sacks, H. Tashiro, D. Towner, C. Tsai, Y. Wang, L. Yang, J.-Y. Yeh, J. Yip, K. Mistry
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  ABSTRACT: A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have been achieved at 1.1 V and off-state leakage of 1 nA/um. Record RF performance for a mainstream 45 nm bulk CMOS technology has been achieved with measured f_T/f_MAX values of 395 GHz/410 GHz for NMOS and 300 GHz/325 GHz for PMOS with 28 nm L_gate transistors. HV I/O transistors with robust reliability and other SOC features, including linear resistors, MIS and MIM capacitors, varactors, inductors, vertical BJTs, precision diodes and high density OTP fuses are employed for HV I/O, analog and RF circuit integration.
  Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
• Source

  Available from: ac.ir

  Conference Proceeding: A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications

  Y. Wang, H. Ahn, U. Bhattacharya, T. Coan, F. Hamzaoglu, W. Hafez, C.-H. Jan, R. Kolar, S. Kulkarni, J. Lin, Y. Ng, I. Post, L. Wel, Y. Zhang, K. Zhang, M. Bohr
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  ABSTRACT: A low-power high-speed SRAM macro is implemented in an ultra-low-power 8M 65nm CMOS for mobile applications. The 1Mb macro features a 0.667μm² low-leakage memory cell and operates with supply voltage from 0.5V to 1.2V. It operates at a frequency of 1.1 GHz at 1.2V and 250MHz at 0.7V. Leakage is reduced to 12μA/Mb at the data retention voltage of 0.5V. The measured bitcell leakage from the SRAM array is ~2pA/b at retention voltage with integrated leakage reduction schemes.
  Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International; 03/2007
• Conference Proceeding: A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications

  I. Post, M. Akbar, G. Curello, S. Gannavaram, W. Hafez, U. Jalan, K. Komeyii, J. Lin, N. Lindert, J. Park, J. Rizk, G. Sacks, C. Tsai, D. Yeh, P. Bai, C.-H. Jan
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  ABSTRACT: Record breaking RF performance was recently achieved on a 65nm CMOS technology (29nm L_gate, 210nm pitch) employing uni-axial strained silicon transistors. These highest-reported cutoff frequencies for NMOS transistors achieve f_T/f_MAX values of 360 GHz/420 GHz. PMOS transistors also demonstrate superior performance with f_T/f_MAX values of 238 GHz/295 GHz. Varactor performance on this substrate technology is also discussed
  Electron Devices Meeting, 2006. IEDM '06. International; 01/2007