ABSTRACT: A new accelerated testing scheme for detecting SRAM bit failure caused by random telegraph noise (RTN) is proposed. By repeatedly monitoring the fail bit count (FBC) under a reduced margin operation condition, increasing trend of FBC along time was clearly observed, which is believed to be caused by RTN. In addition, physics-based ultra-fast Monte Carlo RTN simulation program has been developed, which quantitatively reproduces the test results. By using the simulation calibrated by the test, product reliability against RTN can be accurately predicted.
VLSI Technology (VLSIT), 2010 Symposium on; 07/2010