S. Krishnamoorthy

Publications (2)0 Total impact

• Conference Proceeding: Switching constraint-driven thermal and reliability analysis of Nanometer designs

  S. Krishnamoorthy, V. Venkatraman, Y. Apanovich, T. Burd, A. Daga
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  ABSTRACT: As process technology continues to shrink, interconnect current densities continue to increase, making it ever more difficult to meet chip reliability targets. For microprocessors in the latest 32nm processes, interconnect wear-out via electromigration is as critical a design parameter, if not more so, as timing, power, and area, and must be planned for from the outset. This paper presents a true three-dimensional thermal analysis in order to accurately transform power dissipation into a temperature profile for more accurate reliability estimation at the level of interconnect metal, via resistors and device fingers. This enhancement to prior electromigration analysis flows was a critical enabling technology for deep sub-micron microprocessor design, and will prove only more essential as process technology continues to shrink, and electromigration constraints become ever more restrictive. In addition, the thermal analysis enabled better prediction of device reliability, which we can now calculate and measure the impact of, at the block-level.
  Quality Electronic Design (ISQED), 2011 12th International Symposium on; 04/2011
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  Conference Proceeding: Thermal-aware reliability analysis of nanometer designs

  S. Krishnamoorthy, V. Venkatraman, Y. Apanovich, T. Burd, A. Daga
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  ABSTRACT: Increasing current densities in deep sub-micron designs necessitate accurate power and thermal analysis to help verify compliance with chip-level reliability specifications. This paper presents a thermal-aware analysis flow that accurately captures the effects of design topology, currents, and switching constraints. This static analysis flow demonstrates the need to compute temperature at the level of interconnect metal, via resistors and device fingers, and was used to verify reliability constraints on successive iterations of nanometer-level designs.
  Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conference on; 11/2010