S. Gondi

Oregon State University, Corvallis, OR, United States

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Publications (4)5.3 Total impact

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    ABSTRACT: Supply noise affects the jitter performance of ring oscillator-based phase-locked loops (PLLs) significantly. While the focus of much of the prior art is on supply noise in oscillators, this paper illustrates that supply noise in other building blocks also contribute significantly to PLL output jitter. Analytical expressions for supply-noise sensitivities are derived for each of the circuit blocks used in the PLL and insight into the mechanism through which supply noise appears at the PLL output is provided. Efficient supply-regulation schemes that combine a split-tuned PLL architecture with an optimized low-dropout regulator to achieve better than -22 dB of worst case supply-noise sensitivity for the whole PLL are presented. Fabricated in a 0.18 μm digital CMOS process, the prototype PLL occupies an area of 0.18 μm and operates from a 1.8 V supply. At 1.5 GHz, the total power consumption is 3.3 mW, of which 0.54 mW is consumed in the regulators. The measured output peak-to-peak jitter is 33 ps and 41 ps with no supply noise and with a 100-mV amplitude supply noise tone injected at the worst case noise frequency, respectively.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 12/2010; · 2.24 Impact Factor
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    ABSTRACT: A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. By placing the regulator in the low-bandwidth coarse loop, the proposed PLL architecture allows us to maximize its bandwidth to suppress the oscillator phase noise with neither the power supply-noise rejection nor the power dissipation of the regulator being affected. A replica-based regulator introduces a low-frequency pole in its supply-noise transfer function and avoids degradation of supply-noise rejection beyond the regulator-loop's dominant pole frequency. The prototype PLL fabricated in a 0.18 mum digital CMOS process operates from 0.5 to 2.5 GHz. At 1.5 GHz, the proposed PLL achieves 1.9 ps long-term rms jitter and a worst case supply-noise sensitivity of -28 dB (0.5 rad/V), an improvement of 20 dB over conventional solutions, while consuming 2.2 mA from a 1.8 V supply.
    IEEE Journal of Solid-State Circuits 09/2009; · 3.06 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. The prototype PLL, incorporating a novel regulator, is fabricated in a 0.18 mum digital CMOS process and operates from 0.5 to 2.5 GHz. At 1.5 GHz, the proposed PLL achieves a worst-case noise sensitivity of -28 dB (0.5 rad/V), an improvement of 20 dB over conventional solutions, while consuming 2.2 mA from a 1.8 V supply.
    Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE; 10/2008
  • [Show abstract] [Hide abstract]
    ABSTRACT: Supply-noise significantly affects the jitter performance of ring oscillator-based phase-locked loops (PLLs). While the focus of much of the prior art is on supply-noise in oscillators, this paper illustrates that supply-noise in other building blocks also contribute significantly to PLL output jitter. The current design employs a split-tuned PLL architecture wherein the power supply of the building blocks is derived from the regulated power supply of the VCO. The prototype PLL fabricated in a 0.18 mum digital CMOS process occupies 0.18 mm<sup>2</sup> and consumes only 3.3 mW, from a 1.8 V supply, of which 0.54 mW is consumed in the regulators, while operating at 1.5 GHz. The PLL achieves 33 ps and 41 ps peak-to-peak jitter with no supply noise and with 100 mV peak-to-peak supply noise, respectively.
    Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European; 10/2008

Publication Stats

34 Citations
5.30 Total Impact Points

Institutions

  • 2008–2009
    • Oregon State University
      • School of Electrical Engineering and Computer Science
      Corvallis, OR, United States