C.M. Compagnoni

Politecnico di Milano, Milano, Lombardy, Italy

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Publications (85)104.58 Total impact

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    ABSTRACT: Starting from the theoretical background on the detrapping process in nanoscale Flash memories given in Part I of this paper [1], we address here the effect of idle periods, temperature, and program/erase cycles on the spectral distribution of detrapping events and, in turn, on threshold-voltage instabilities appearing during a data retention time stretch. In so doing, we come to a comprehensive model able to deal with threshold-voltage instabilities from whatever on-field usage or testing scheme of the memory array, carefully accounting for both charge trapping and detrapping, and reproducing distributed-cycling effects. The model represents a valuable tool for the predictive reliability analysis of Flash technologies and for the development of accelerated experimental schemes for the assessment of post-cycling thereshold-voltage instabilities coming from charge detrapping.
    IEEE Transactions on Electron Devices 01/2014; 61(8):2811-2819. · 2.06 Impact Factor
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    ABSTRACT: This letter discusses the working principles of a memory cell exploiting the bistability of a single nanoscale gated-thyristor to achieve high-performance DRAM operation (T-RAM cell). The device relies on the possibility to reach either of the two stable states of the thyristor by means of a fast low-to-high gate switch and depending on the amount of holes in the gated (p) -base. In particular, with proper selection of the low and high gate levels, the stationary hole concentration in the (p) -base leads the thyristor to its high current state while hole depletion results in an orders-of-magnitude lower anode current. This opens the possibility for a DRAM technology with a simple back-end process and fast write and read operations with low voltage requirements.
    IEEE Electron Device Letters 01/2014; 35(9):921-923. · 2.79 Impact Factor
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    ABSTRACT: This paper and the corresponding Part II [1] revisit charge trapping and detrapping in Flash memories considering some major features of the phenomenon which have been clearly detected on nanoscale technologies: charge discreteness, statistical charge capture and emission, statistical distribution of the threshold-voltage shift following a charge capture/emission event, and spectral distribution of the detrapping time constants over many decades of time. In this Part I, we address threshold-voltage instabilities following charge detrapping from the cell tunnel oxide, highlighting their statistical properties and coming to a powerful formula for their quantitative analysis. These results pave the way to the development of a comprehensive statistical model able to deal with charge trapping/detrapping during whatever on-field array operation, representing the topic of Part II.
    IEEE Transactions on Electron Devices 01/2014; 61(8):2802-2810. · 2.06 Impact Factor
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    ABSTRACT: This paper presents a numerical investigation of the random telegraph noise amplitude in nanoscale MOS devices based on the statistical impedance field method. This method allows a strong reduction of the computational burdens required for the calculation of the amplitude statistics with respect to conventional Monte Carlo models based on the numerical implementation of microscopic differences on the simulated device structure, allowing the exploration of lower probability levels. Despite a rather good estimation of the amplitude statistics, however, the method results in relevant inaccuracies when looking at the single Monte Carlo samples, due to the linear approximations involved.
    Journal of Computational Electronics 12/2013; 12(4):585-591. · 1.01 Impact Factor
  • A. Maconi, C.M. Compagnoni, A.S. Spinelli, A.L. Lacaita
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    ABSTRACT: This paper presents a detailed simulation analysis of the erase performance of junction-less charge-trap memory arrays in the cylindrical geometry, showing that a saturation of the erased threshold voltage occurs as a result of incomplete inversion of the intercell regions when positive charge is stored in the cells. This erase saturation issue is investigated as a function of string and cell parameters, revealing lower erase capabilities for large cell-to-cell separation, small substrate radius, and small equivalent-oxide thickness of the gate stack. These results add new constraints to the design of cylindrical junction-less memory technologies.
    IEEE Transactions on Electron Devices 01/2013; 60(7):2203-2208. · 2.06 Impact Factor
  • Source
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    ABSTRACT: This letter presents a numerical investigation of the statistical distribution of the random telegraph noise (RTN) amplitude in nanoscale MOS devices, focusing on the change of its main features when moving from the subthreshold to the on-state conduction regime. Results show that while the distribution can be well approximated by an exponential behavior in subthreshold, large deviations from this behavior appear when moving toward the on-state regime, despite a low probability exponential tail at high RTN amplitudes being preserved. The average value of the distribution is shown to keep an inverse proportionality to channel area, while the slope of the high-amplitude exponential tail changes its dependence on device width, length, and doping when moving from subthreshold to on-state.
    IEEE Electron Device Letters 01/2013; 34(5):683-685. · 2.79 Impact Factor
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    ABSTRACT: This work investigates the performance of the statistical impedance field method in the analysis of the amplitude of random telegraph noise fluctuations in nanoscale MOS devices. Considering different channel doping profiles, we show that this method offers a practical compromise between accuracy and computational loads, allowing a good assessment of the RTN amplitude statistics while resulting in non-negligible errors on the single microscopic samples where atomistic doping strongly contributes to non-uniformities of channel inversion and to percolative source-to-drain conduction.
    Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on; 01/2013
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    ABSTRACT: This work is focused on the accelerated testing of Flash memory reliability, taking our 45 nm NOR technology as a case study to highlight some major issues that may affect the investigation of modern nanoscale devices. In particular, results will be shown on cycling-induced threshold-voltage instabilities coming from charge trapping/detrapping in the cell tunnel oxide during post-cycling data retention or bake experiments, whose characterization relies on the possibility to reduce the experimental time by an increase of the test temperature according to an Arrhenius law via an activation energy EA. These accelerated characterization schemes come from a detailed physical understanding and modeling of the damage creation/recovery dynamics and rely on the careful evaluation of EA. As shown in the case of the investigated NOR technology, this often does not represent a trivial task, due to the large number of spurious effects affecting the threshold voltage of nanoscale memory cells.
    IC Design & Technology (ICICDT), 2013 International Conference on; 01/2013
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    ABSTRACT: This paper investigates the limitations to the accuracy and the main issues of the spectroscopic analyses of random telegraph noise (RTN) traps in nanoscale MOSFETs. First, the impact of the major variability sources affecting decananometer MOSFET performance on both the RTN time constants and the trap depth estimation is studied as a function of the gate overdrive. Results reveal that atomistic doping and metal gate granularity broaden the statistical distribution of the RTN time constants far more than what comes from the random position of the RTN trap in the 3-D device electrostatics, contributing, in turn, to a significant reduction of the accuracy of trap spectroscopy. The accuracy is shown to improve the higher is the gate overdrive, owing to a more uniform and gate-bias-independent surface potential in the channel, with, however, the possible drawback of triggering the simultaneous trap interaction with both the channel and the gate. This simultaneous interaction is, finally, shown to critically compromise trap spectroscopy in thin-oxide devices.
    IEEE Transactions on Electron Devices 01/2013; 60(2):833-839. · 2.06 Impact Factor
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    ABSTRACT: This paper presents a detailed experimental and numerical investigation of the variability of the band-to-band leakage current of p-n junctions in nanoscale MOS devices. The experimental results reveal that this leakage follows a log-normal statistical distribution, whose spread, barely affected by temperature, increases as junction scaling proceeds. These features are correctly reproduced by 3-D device simulations, whose results allow to identify in atomistic doping the main origin of the leakage statistical dispersion.
    IEEE Transactions on Electron Devices 01/2013; 60(10):3291-3297. · 2.06 Impact Factor
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    ABSTRACT: We report the first experimental evidence of discrete threshold-voltage transients on high-density NAND Flash arrays during post-cycling data retention. Proper choice of experimental conditions eliminates the impact of averaging effects and disturbs on the transients, enabling clear detection of single charge emission events from/to the tunnel oxide of sub-30nm NAND Flash cells. A stochastic model for the discrete emission process was developed from experimental data, demonstrating that number fluctuation of charges trapped in the tunnel oxide and the statistical nature of their emission dynamics strongly affect the post-cycling data retention performance of the arrays. These results pave the way for further analyses of NAND Flash reliability, where the behavior of single electrons and defects can be monitored and facilitate detailed assessments of the fundamental scaling challenges arising from the discrete nature of charge trapping/detrapping.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: This paper shows that the reliability characterization of nanoscale Flash memories requires an accurate control of the adopted experimental tests, preventing spurious issues to emerge and alter the basic conclusions on the investigated reliability constraints. To this aim, the paper reports a case study on a 45-nm NOR technology, where the experimental investigation of the activation energy for damage recovery during post-cycling bakes and of distributed-cycling effects is substantially affected by parasitic threshold-voltage (VT) drifts, activated by the repeated acquisition of the whole array VT map during the experiment. Only when this spurious effect is taken into account, the typical 1.1-eV activation energy for damage recovery and the effectiveness of the conventional distributed-cycling schemes are correctly demonstrated on the investigated technology.
    IEEE Transactions on Device and Materials Reliability 01/2013; 13(2):362-369. · 1.52 Impact Factor
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    ABSTRACT: This letter presents a detailed experimental investigation of the current-voltage characteristics of deca-nanometer gated-thyristors, highlighting that strong differences exist between the static and the dynamic operation of these devices. In particular, results reveal that the forward-breakover voltage determining thyristor turn-on does not depend only on the applied gate voltage, but also on the rise time of the applied gate pulse, decreasing for fast pulse fronts. This is explained in terms of a higher electron injection from the cathode to the anode triggering device turn-on when the gate switching time is shorter than that required for holes to leave the p-base.
    IEEE Electron Device Letters 01/2013; 34(5):629-631. · 2.79 Impact Factor
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    ABSTRACT: This paper presents a comprehensive numerical study of the impact of cell shape on random telegraph noise (RTN) in nanoscale Flash memory devices. The statistical dispersion of the RTN fluctuation amplitude is computed using both classical and quantum-corrected 3-D TCAD simulations of devices featuring three different active-area shapes (planar, rounded edges, and full rounded), with self-aligned or surrounding floating gate. For both the floating-gate geometries, results show that RTN immunity is enhanced by increasing the rounding of the active-area edges in the width direction, due to a more uniform source-to-drain conduction during read. For this analysis, the importance of quantum-mechanical corrections for the correct evaluation of the RTN distribution of sharp-edge devices is highlighted. Finally, the reduction of RTN by cell shape engineering is shown to be anticorrelated with the reduction of cell threshold-voltage variability.
    IEEE Transactions on Electron Devices 10/2012; 59(10):2774-2779. · 2.06 Impact Factor
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    ABSTRACT: This paper presents a detailed simulation analysis of the impact of 3-D electrostatics and atomistic doping on the variability of the random telegraph noise (RTN) time constants in nanoscale MOS devices. Results on a template decananometer Flash cell show that both the effects contribute to a large statistical dispersion of the capture/emission time constants of oxide traps placed at the same distance from the silicon surface, mainly due to nonuniform channel inversion. The statistical dispersion has an orders-of-magnitude increase when moving from the on-state to the subthreshold cell regimes and has major implications on the spectroscopic investigation of RTN traps, as will be discussed in Part II of this work.
    IEEE Transactions on Electron Devices 09/2012; 59(9):2488-2494. · 2.06 Impact Factor
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    ABSTRACT: This paper investigates the impact of 3-D electrostatics and atomistic doping on the spectroscopic analysis of random telegraph noise (RTN) traps in nanoscale MOS devices. Using the numerical model and the template decananometer Flash cell presented in Part I of this paper, the gate bias dependence of the capture and emission time constants of oxide traps is shown to largely depend on the trap position over the channel, both in the subthreshold and in the on-state regime. This compromises the accuracy of any 1-D method for trap spectroscopy based on the time constants analysis and, due to the randomness in trap position and dopant placement in the substrate, calls into question the possibility for any accurate trap spectroscopy in nanoscale devices. Finally, the possibility to extract any information on the trap depth from the fluctuation amplitude of RTN waveforms is shown to be precluded by the large statistical spread of the amplitude itself, resulting in its negligible correlation with the trap position in the oxide and with the waveform time constants.
    IEEE Transactions on Electron Devices 09/2012; 59(9):2495-2500. · 2.06 Impact Factor
  • Andrea Ghetti, Salvatore Maria Amoroso, Aurelio Mauri, Christian Monzio Compagnoni
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    ABSTRACT: This paper presents a thorough numerical investigation of the effect of nonuniform doping on random telegraph noise (RTN) in nanoscale Flash memory devices. For a fixed average threshold voltage, the statistical distribution of the RTN fluctuation amplitude is studied with nonconstant doping concentrations in the length, width, or depth direction in the channel, showing that doping increase at the active area corners and retrograde and $\delta$-shape dopings appear as the most promising profiles for RTN suppression. In particular, the improvements offered by retrograde and $ \delta$-shape dopings increase the more the high doping regions are pushed far from the channel surface due to a more uniform source-to-drain conduction during read. Finally, the suppression of RTN by engineered doping profiles is correlated with the reduction in cell threshold voltage variability.
    IEEE Transactions on Electron Devices 01/2012; 59(2):309-315. · 2.06 Impact Factor
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    ABSTRACT: We present a self-consistent 2-D quantum-mechanical model for charge distribution in cylindrical gate-all-around devices with computation of the gate tunneling current. The validity of 1-D approximations for the charge and the gate current is discussed, assessing the validity of a previously proposed analytical approximation for the tunneling current in the Fowler-Nordheim regime.
    IEEE Transactions on Electron Devices 01/2012; 59(7):1837-1843. · 2.06 Impact Factor
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    ABSTRACT: This paper presents a detailed compact-modeling investigation of the string current in decananometer nand Flash arrays. This investigation allows, first of all, to highlight the role of velocity saturation, low-field mobility, and drain-induced barrier lowering on the string current versus read voltage characteristics. Results are validated on a 41-nm technology for different positions of the selected cell along the nand string, different pass voltages, and different array background patterns. The effect of cycling on the string current is then investigated by means of postcycling bake experiments, showing that the impact of charge trapping/detrapping and interface state generation/annealing varies as a function of the read current level. Compact-modeling results display that, at low read currents, charge trapping/detrapping represents the main damage mechanism for the cells, while interface states come into play for read currents close to the string saturation level via mobility degradation.
    IEEE Transactions on Electron Devices 01/2012; 59(9):2331-2337. · 2.06 Impact Factor
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    ABSTRACT: This paper investigates the validity of distributed-cycling schemes on scaled Flash memory technologies. These schemes rely on the possibility to emulate on-field device operation by increasing the cycling temperature according to an Arrhenius law, but the assessment of the activation energy that has to be used on scaled technologies requires a careful control of the experimental tests, preventing spurious second-order effects to emerge. In particular, long gate-stresses required to gather the array threshold voltage (VT) map are shown to give rise to parasitic VT-drifts, which add to the VT-loss coming from damage recovery during post-cycling bake. When the superposition of the two phenomena is taken into account, the effectiveness of the conventional qualification schemes relying on a 1.1 eV activation energy is fully confirmed at the 45 nm NOR node.
    Reliability Physics Symposium (IRPS), 2012 IEEE International; 01/2012