P. Tessariol

Politecnico di Milano, Milano, Lombardy, Italy

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Publications (8)5.22 Total impact

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    ABSTRACT: The aim of this work is to investigate the physical mechanisms behind the write/erase and retention performances of band gap engineering (BE) layers used as tunnel oxide in charge trap memory stack. The investigation of the BE layers alone will be completed with the analyses of its integration within a TANOS (TaN/Alumina/Nitride/Oxide/Silicon) stack, pointing out the correlation between electrical performance and reliability limits.Good write/erase/retention performances can be achieved with BE tunnel oxide by using silicon nitride layer integrated in SiO2–Si3N4–SiO2 stack, as long as all different mechanisms are taken into account in optimizing stack composition: hole injection which improves erase efficiency, charge trapping and de-trapping from the thin silicon nitride which causes program instabilities and initial charge loss which does not significantly impact long term retention. All these phenomena make very crucial the BE tunnel process control and difficult its use for multi-level application.
    Microelectronic Engineering 07/2011; 88(7):1182-1185. DOI:10.1016/j.mee.2011.03.072 · 1.20 Impact Factor
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    ABSTRACT: The aim of this work is to understand charge loss mechanisms in TANOS stack for which charge retention is monitored just after programming in an almost continuous way and voltage is applied during retention experiments in order to obtain zero electric field either on alumina or tunnel oxide. The charge loss mechanisms in TANOS stack can be a quite complicated process: An initial fast DT from interface traps localized at SiN/alumina interface, followed by charge loss through alumina from bulk traps in SiN which influences charge redistribution towards the tunnel oxide, observed only in Si-rich SiN. Programming voltage and stack composition impact trapped charge localization and hence charge redistribution and charge loss, even if the same initial Vfb is considered in charge retention experiments. While the charge loss through tunnel oxide is a DT, the charge loss through alumina depends on temperature and it is the main component of the charge loss in retention experiments for longer time.
    Journal of vacuum science & technology. B, Microelectronics and nanometer structures: processing, measurement, and phenomena: an official journal of the American Vacuum Society 02/2011; 29(1-29):01AE01 - 01AE01-4. DOI:10.1116/1.3532541 · 1.46 Impact Factor
  • Rino Micheloni · Luca Crippa · Alessandro Grossi · Paolo Tessariol ·
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    ABSTRACT: NAND Flash memory has become the preferred nonvolatile choice for portable consumer electronic devices. Features such as high density, low cost, and fast write times make NAND perfectly suited for media applications where large files of sequential data need to be loaded into the memory quickly and repeatedly. This chapter starts with an overview of the basic functionalities of the NAND Flash storage. Popular devices like Flash cards are then described as an example of NAND-based systems. The last part of this chapter deals with all the state-of-the-art technologies used to reduce the equivalent bit size. In particular, the reader will find an overview of the multilevel storage and of the 3D solutions from single-die 3D architectures to packages containing multiple dies.
    Memory Mass Storage, 01/2011: pages 289-334; , ISBN: 978-3-642-14751-7
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    ABSTRACT: This paper presents a detailed investigation of the ISPP dynamics of charge-trap memory capacitors, considering not only the flat-band voltage but also the bottom oxide electric field and tunneling current evolution during programming. Differently from the floating-gate case, results on nitride-based memories show that the flat-band increase per step does not equal the step amplitude of the gate staircase, decreasing, moreover, as programming proceeds. As a consequence, the electric field and tunneling current through the bottom oxide are shown to largely increase. Using results at different temperatures and on samples with different stack compositions, this dynamics is explained in terms of a drop of the programming efficiency as more and more charge is stored in the nitride layer, due to the reduction of the number of free traps available for capturing the injected electrons.
    Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European; 10/2010
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    ABSTRACT: In this work we present a detailed investigation of TANOS memory reliability, focusing on issues raised by Al<sub>2</sub>O<sub>3</sub> trapping/detrapping and leakage. These effects are investigated as a function of alumina thickness, electric field and temperature, comparing experimental and modeling results for trap parameters extraction. For TANOS devices, Al<sub>2</sub>O<sub>3</sub> charge storage modifies program and erase saturation level particularly when higher Al<sub>2</sub>O<sub>3</sub> thikness are considered. Threshold instability in early steps for endurance and retarded behavior for retention can be also ascribed to the Al<sub>2</sub>O<sub>3</sub> trapping. Moreover, Al<sub>2</sub>O<sub>3</sub> layer has been shown to provide the main leakage path for bottom oxides thickness in the 4.5 nm or above range.
    Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
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    ABSTRACT: We present a comprehensive investigation of the programming dynamics of nanoscale charge-trap memories, based on 3D Monte Carlo simulations accounting for: 1) true 3D electro-statics during programming and read; 2) atomistic substrate doping; 3) discrete traps, fluctuating in number and position, with localized electron storage; 4) discrete electron injection into traps. The model allows to clarify several key issues affecting the program operation of charge-trap memories, most notably the reduced slope of the ISPP transients exhibited by scaled cells, the programming variability, and the width of the final programmed threshold-voltage distribution. Results are of utmost importance for the assessment of the true programming performance of nanoscale charge-trap memory technologies.
    Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International 01/2010; DOI:10.1109/IEDM.2010.5703415
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    ABSTRACT: The aim of this work is to investigate the physical mechanisms behind TANOS (TaN/Alumina/Nitride/Oxide/Silicon) cycling degradation. A comparison of the degradation induced in the TANOS stack by unipolar or bipolar stress has allowed the separation the different degradation contributions. A comparison with standard floating gate (FG) stack has also been carried out to confirm these degradation mechanisms. Finally, different stack configurations are reported, showing the key factors affecting the degradation and giving trends for improving cycling degradation.
    Microelectronic Engineering 07/2009; 86(7):1822-1825. DOI:10.1016/j.mee.2009.03.041 · 1.20 Impact Factor
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    ABSTRACT: The aim of this work is to study the impact of silicon nitride deposition/treatment technologies on charge trap (CT) nonvolatile memory performances. The authors have found that the technology modifies the charge trapping behavior with a one to one correlation between write/erase and charge retention characteristics. In particular, they used rapid thermal chemical vapor deposition techniques to obtain films with different compositions, but they were not able to improve CT performances with respect to standard low pressure chemical vapor deposition (LPCVD). Besides, an in situ steam generated treatment applied to standard LPCVD silicon nitride modifies the film properties inducing a lower programming efficiency, but improving charge retention characteristics.
    Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures 01/2009; 27(1). DOI:10.1116/1.3025836 · 1.36 Impact Factor