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ABSTRACT: In this paper, we present an approach to constrained automatic test pattern generation (ATPG) for functional circuits at register-transfer level (RTL) with the help of a design-for-testability (DFT) technique called F-scan. The DFT method optimally utilizes existing functional elements and paths for test, thus it effectively reduces the hardware overhead due to test. This is done by arranging all registers in the circuit into F-scan-paths and augmenting necessary circuitry at RTL. After DFT, we create the constraint test generation model of the circuit based on the test environment obtained from the information of F-scan-paths. With this approach, only the applicable test vectors to the F-scan-paths can be generated and test application time is kept at the minimum. The comparison of F-scan with the performance of gate-level full scan design is shown through the experimental results.
Test Conference (ITC), 2010 IEEE International; 12/2010
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ABSTRACT: Today's digital circuits demand both high speed performance and miniaturization of chip size. As a result, delay fault testing has become very important to verify the quality requirements of VLSI chips. Full scan has been used to generate test patterns that achieves high fault coverage, of which the standard techniques for delay scan testing are skewed-load and broad-side. However, as the circuits become larger, using full scan can be very costly due to high area overhead and long test application time. In this paper, we apply delay fault automatic test pattern generation (ATPG) on F-scannable circuits. In our previous work, we have shown the strengths of F-scan compared with full scan in terms of area overhead, test application time, and fault coverage. We utilize the advantages of F-scan to solve the current problems of skewed-load and broad-side. The proposed method is to utilize a hybrid model for F-scannable circuits in generating test patterns, wherein a fast scan enable signal used by skewed-load technique is not required. Transition delay fault coverage achieved by this approach is equal to or higher than that achieved by both skewed-load and broadside approaches for gate-level full scan. This is proven through our experiments on ITC'99 benchmark circuits.
Communications and Information Technologies (ISCIT), 2010 International Symposium on; 11/2010
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ABSTRACT: This paper presents a new methodology for functional register transfer level (RTL) scan, in which existing functional elements and paths can be maximally utilized. The approach is called F-scan, which primarily aims to reduce the total area overhead due to augmentation for testing. Since the method allows for parallel scanning of test vectors, test application time is also made to be at the minimum. The case study shows the effectiveness of our approach compared to full scan design.
ASIC, 2009. ASICON '09. IEEE 8th International Conference on; 11/2009
