[Show abstract][Hide abstract] ABSTRACT: In this paper, we propose a real-time virtual re-convergence hardware platform especially to reduce the visual fatigue caused by stereoscopy. Our unique idea to reduce visual fatigue is to utilize the virtual re-convergence based on the optimized disparity-map that contains more depth information in the negative disparity area than in the positive area. Our virtual re-convergence hardware platform, which consists of image rectification, disparity estimation, depth post-processing, and virtual view control, is realized in real time with 60 fps on a single Xilinx Virtex-5 FPGA chip.
Journal of Semiconductor Technology and Science 06/2012; 12(2). DOI:10.5573/JSTS.2012.12.2.127 · 0.52 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Nowadays, 3D-image processing of stereovision that uses two camera lenses has been a vibrant research filed. This paper proposes an efficient hardware architecture for high performance and real-time smoothing filter that is applicable to enhance the disparity map image from 3D stereovision system. First, we maximally utilized the parallel and pipeline operations. Second, we adopted 11 by 11 sparse mask operations instead of using the 33 by 33 window to achieve faster processing time without sacrificing the quality obtained from 33 by 33 mask operation. Furthermore, our architecture showed faster in processing time and smaller in errors on the images, compared with the normal 33 by 33 mean filter. Our verification was accomplished on the Virtex5 XC5VLX330 FF1760 FPGA of Xilinx with using 100MHz system clock. In a 1280 by 720 video frames, our verification shows that the real-time image was processed with 325fps. Our achievement shows remarkably higher operation rates than the existing ordinary mean filtering method.
Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on; 09/2011
[Show abstract][Hide abstract] ABSTRACT: In our related work, we proposed Cognitive Stereo Auto Focus for stereo camera. Instead of moving optical axis, Cognitive Stereo Auto Focus shifts one side image to the opposite side for setting focus. In the shifting process, focus point should be set on the proper place not to cause any side effect produced by visual fatigue to user. To perform low visual fatigue focusing, Cognitive Stereo Auto Focus analyzes the input scene and find how many objects are in the image and how big they are. Based on the analysis information, the algorithm sets the focus where user feels less visual fatigue. In this paper, we suggest a mass object analyzer hardware whose objective is analyzing disparity map for generating information on the objects in the scene for Cognitive Stereo Auto Focus. Through experiment results, we confirmed that the performance of the suggested system is enough for practical use.
[Show abstract][Hide abstract] ABSTRACT: In this paper, a new hardware implementation for the real time disparity map is presented. The real time disparity map includes the Dynamic Search Range Estimation, Disparity estimation, and Error Correction. Our demonstrated design flow shows an approach to implementation and hardware architecture of real-time disparity map estimation. This design is efficiently synthesized on Xilinx vertex 5 VLX 330 FPGA. The resulting hardware implementation is analyzed and simulated for system clock speed 100MHz to verify adequate performance. Since the algorithm is not so complicated to adapt real-time hardware design, we successfully made system with FPGA Prototype design.
[Show abstract][Hide abstract] ABSTRACT: As requirements of 3D contents have been increased, a matching algorithm to obtain a disparity-map becomes vibrant research field. This processing includes a multi-sliding-window-operation (MSWO) which requires high memory and processing-time consumption. In this paper, we propose an effective hardware architecture with convergence of on-chip memory and shift registers, and parallelized cores. We utilize census as a matching algorithm and a 7 by 7 window in a 160 by 90 image, with search range length of 42. We synthesize on Vertex 5 from Xilinx, operating at 100 MHz clock. Our proposed method has lower memory consumption, and search range length times faster than previous one.