Hojung Kim,
Sanghun Jeon,
Myoung-Jae Lee,
Jaechul Park,
Sangbeom Kang,
Hyun-Sik Choi,
Churoo Park,
Hong-Sun Hwang,
Changjung Kim, Jaikwang Shin,
U-In Chung
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ABSTRACT: The three-dimensionally alternating integration of stackable logic devices with memory cells represents a revolutionary approach to the fabrication of extremely high density memory devices. Conventional silicon-based memory devices face impending limits if they are progressively scaled toward smaller-sized features. Here, we present a high-density memory architecture that utilizes electronically active oxide thin-film transistors (TFTs) combined with memory elements such as vertical NAND and resistive random access memory devices. High-mobility [~μ<sub>saturation</sub> of 20 cm<sup>2</sup>/(eV·s)] oxide TFTs with amorphous Hf-In-Zn-O performs fairly well as a decoder, a driver, a sense amplifier, and a latch, and the core elements that are required for 3-D logic circuits. With these logic circuit elements, memory density can be considerably increased up to tens of terabits due to the significantly reduced interconnection lines and logic circuit areas in the bottom silicon layer. This approach can serve as a useful strategy for the development of high-density memory devices.
IEEE Transactions on Electron Devices 12/2011; · 2.32 Impact Factor
