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ABSTRACT: This study presents an ultra-low-power 24 GHz low-noise amplifier (LNA) using 0.13 μm CMOS technology. We propose of using the minimum noise measure (M<sub>MIN</sub>) as the guideline to determine the optimal bias and geometry of the transistors in the circuit. The power-constrained simultaneous noise and input matching (PCSNIM) technique is also employed for this design. With the proposed design approach, the LNA achieves a peak gain of 9.2 dB and a minimum NF of 3.7 dB under a supply voltage of 1 V. The associated power consumption is only 2.78 mW.
IEEE Microwave and Wireless Components Letters 01/2011; · 1.72 Impact Factor
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ABSTRACT: This paper studies the electrostatic discharge (ESD)-protected RF low-noise amplifiers (LNAs) in 65-nm CMOS technology. Three different ESD designs, including double-diode, modified silicon-controlled rectifier (SCR), and modified-SCR with double-diode configurations, are employed to realize ESD-protected LNAs at 5.8 GHz. By using the modified-SCR in conjunction with double-diode, a 5.8-GHz LNA with multiple ESD current paths demonstrates a 4.3-A transmission line pulse (TLP) failure level, corresponding to a ~ 6.5-kV Human-Body-Mode (HBM) ESD protection level. Under a supply voltage of 1.2 V and a drain current of 6.5 mA, the proposed ESD-protected LNA demonstrates a noise figure of 2.57 dB with an associated power gain of 16.7 dB. The input third-order intercept point (IIP3) is - 11 dBm, the input and output return losses are greater than 15.9 and 20 dB, respectively.
IEEE Transactions on Microwave Theory and Techniques 01/2011; · 1.85 Impact Factor
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ABSTRACT: A compact ultra-wideband low-noise amplifier (LNA) with a 12.4-dB maximum gain, a 2.7-dB minimum noise figure (NF), and a bandwidth over 0.1-14 GHz is realized in a 0.13-μm CMOS technology. The circuit is basically an inductorless configuration using the resistive-feedback and current-reuse techniques for wideband and high-gain characteristics. It was found that a small inductor of only 0.4 nH can greatly improve the circuit performance, which enhances the bandwidth by 23%, and reduces the NF by 0.94 dB (at 10.6 GHz), while only consuming an additional area of 80 × 80 μm<sup>2</sup>. The LNA only occupies a core area of 0.031 mm , and consumes 14.4 mW from a 1.8-V supply.
IEEE Transactions on Microwave Theory and Techniques 11/2010; · 1.85 Impact Factor
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ABSTRACT: A V-band Miller frequency divider with a locking range of 15.7 GHz (f<sub>0</sub> = 64 GHz) is realized in 0.13 μm CMOS technology. Using the proposed transformer-injection technique, the signal can be injected into the mixer core directly without the current and impedance limitations of the input stage. The divider also features a fully differential topology. Under the condition of V<sub>DD</sub> = 0.9 V, the divider can even function with a power dissipation of only 0.81 mW.
IEEE Microwave and Wireless Components Letters 08/2010; · 1.72 Impact Factor
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ABSTRACT: This study presents a wideband low noise amplifier (LNA) including electrostatic discharge (ESD) protection circuits using 65 nm CMOS with a gate oxide thickness of only ~ 2 nm. By co-designing the ESD blocks with the core circuit, the LNA shows almost no performance degradation compared to the reference design without ESD. Under a power consumption of only 6.8 mW, the silicon results show that the LNA can achieve a peak power gain of 13.8 dB. Within the 3 dB bandwidth from 2.6 GHz to 6.6 GHz, the noise figure (NF) is in a range of 4.0 dB to 6.5 dB and the input reflection coefficient S <sub>11</sub> is below -13.0 dB. Using the miniaturized Shallow-Trench-Isolation (STI) diode of ~ 40 fF capacitance and a robust gate-driven power clamp configuration, the proposed LNA demonstrates an excellent 4 kV human body mode (HBM) ESD performance, which has the highest voltage/capacitance ratio ( ~ 100 V/fF) among the published results for RF LNA applications.
IEEE Microwave and Wireless Components Letters 12/2009; · 1.72 Impact Factor
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ABSTRACT: By means of co-design ESD protection circuit as the low noise amplifier (LNA) input matching network, a 5.8-GHz LNA with excellent ESD and noise performances is demonstrated by a 65-nm CMOS technology. The diode-based ESD design with a power clamp can achieve 4 kV human body model (HBM) performance while the noise figure (NF) is only 0.05 dB higher than that of the LNA without the extra ESD blocks. Under a supply voltage of 1.2 V and drain current of 7 mA, the ESD-LNA has a NF of 1.9 dB with an associated power gain of 18 dB. The input third-order intercept point (IIP3) is -11 dBm and the input and output insertion losses are below -16 dB and -20 dB, respectively.
Microwave Symposium Digest, 2009. MTT '09. IEEE MTT-S International; 07/2009
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ABSTRACT: A 10-Gb/s current mode logic (CML) input/output (I/O) circuit for backplane interconnect is fabricated in 0.18-mu m 1P6M CMOS process. Comparing with conventional I/O circuit, this work consists of input equalizer, limiting amplifier with active-load inductive peaking, duty cycle correction and CML output buffer. To enhance circuit bandwidth for 10-GB/s operation, several techniques include active load inductive peaking and active feedback with current buffer in Cherry-Hooper topology. With these techniques, it reduces 30%-65% of the chip area comparing with on-chip inductor peaking method. This design also passes the interoperability test with switch fabric successfully. It provides 600- mV<sub>pp</sub> differential voltage swing in driving 50-Omega output loads, 40-dB input dynamic range, 40-dB voltage gain, and 8-mV input sensitivity. The total power consumption is only 85 mW in 1.8-V supply and the chip feature die size is 700 mum times 400 mum.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 06/2009; · 1.22 Impact Factor
