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Publications (11)0 Total impact

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    ABSTRACT: We present a study on NBTI life time for high voltage PMOS transistors. These devices are used in erasing and programming control circuits for a floating-gate flash based FPGA array fabricated with a 65nm embedded process. NBTI stress tests were performed with different gate biases and at different temperatures. Life time model parameters, such as voltage acceleration factor and activation energy, were obtained from the tested results. NBTI device life time was assessed against product requirements. A 50 times (50X) margin in life time was estimated for our baseline process, based on DC stress data. Longer AC life time is seen due to recovery of device degradation. This allows even more margin for the real operation. Interface trap and positive charge contributions to the observed Vt shift were separated from a recovery study. It is observed that interface traps can be recovered either partially or completely depending on the recovery temperature. Positive charges can only be partially recovered at positive gate biases. To further improve NBTI lifetime margin against product requirement, LDD doping was increased and optimized. We are able to further improve HV PMOS device performance in this regard.
    Physical and Failure Analysis of Integrated Circuits (IPFA), 2013 20th IEEE International Symposium on the; 01/2013
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    ABSTRACT: In this work, HCI effect of PMOS FETs was studied. For a given drain bias, electron trapping is the dominant degradation mechanism for a gate bias close to 20% of the drain bias. A maximum gate current is seen under this bias condition. Hole trapping is dominant when the gate bias is equal to the drain bias where drain current is the maximum. Electron trapping enhances PMOS driving current or Idsat whereas hole trapping degrades Idsat. The effect of electron trapping and hole trapping cancel each other. As a result, life time is longer when two trapping mechanisms are involved compared with the life time with one trapping mechanism. In this study, device Idsat degradation was measured with different gate and drain biases in a DC mode. An AC stress is also performed in which gate/drain bias waveforms follow those of a typical switching inverter. Due to the above-mentioned cancelling effect, PMOS HCI AC life time is longer and the DC to AC conversion factor is much larger than conventionally used values. The effect of STI stress on HCI degradation is briefly studied. Layouts to minimize this effect are then proposed.
    Physical and Failure Analysis of Integrated Circuits (IPFA), 2013 20th IEEE International Symposium on the; 01/2013
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    ABSTRACT: We present studies of an extrinsic program disturb mechanism in a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. It is concluded that multiple positive charges are involved during disturb to explain the observed extrinsic behavior. Its failure rate was improved with tunnel oxidation process tuning and stronger pre-oxidation cleans.
    Integrated Reliability Workshop Final Report (IRW), 2012 IEEE International; 01/2012
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    ABSTRACT: We present a highly reliable Flash based FPGA fabricated with a 65nm embedded process. A very robust ON and OFF Vt window, over 8V, has been achieved with tight cell to cell distributions. 1k program/erase cycles have been performed and charge trap induced Vt window loss is less than 0.2V. Some initial Vt shift is seen at erase side after retention bake. The shift saturates after 24 hours and the post-bake Vt window is close to 8V. There is still a 2V margin from our design spec which is 6V. Operation disturb life time was extrapolated from an accelerated test. AC life time is greater than 2000 years. For some high security applications we provide a user-verify feature. Based on accelerated testing we have proposed the number of user verifies and predicted the error rate.
    Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on; 01/2012
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    ABSTRACT: We present a study of the disturb mechanism encountered in a novel user verify technique that can be used to enhance the security of a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. Two disturb mechanisms are studied in detail. The intrinsic disturb mode is related to Fowler-Nordheim (FN) tunneling, whereas an extrinsic disturb mode involves traps which enhance the tunneling probability. The effect of single and multiple positive charges is simulated. It is concluded that multiple charges are involved during disturb to explain the observed extrinsic behavior. Accelerated testing predicts that 10k verify operations can be performed with an error rate less than 1ppm for a five million gate FPGA, equivalent to a FIT rate of approx. 0.001 failures per 109 hours per million gates when applied over a 20 year lifetime. The low verify-induced error rate makes the technique suitable for enhancing security by providing timely detection of malicious tampering attacks.
    01/2011;
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    ABSTRACT: High speed array architecture and cell optimization in the Uniform Channel Program and Erase (UCPE) floating gate 2 transistor (2T)-embedded flash cell (eFlash) are investigated. It is important to optimize select gate (SG) channel length from 2T-eFlash test array when CG flash device width/length and SG length are pre-determined by other constraints. SG-punch through (PT) driven Gate Disturb (GD) and Gate Induced Drain Leakage current (GIDL) driven GD must be simultaneously studied to determine the optimum CG and SG spacing. For the applications requiring thick tunnel oxide (10 nm) such as automotive products, the conductivities of the Sector Select Gate (SSG) device and Control Gate (CG) flash device are critical for read performance. A double SSG scheme per sector and common metal source line architecture were introduced. In this paper, we report our investigation results to optimize 2T eFlash cell design and array architecture to achieve high performance eFlash operation without sacrificing reliability within the constraint of embedding a flash process in the 65 nm standard logic process.
    Memory Workshop (IMW), 2010 IEEE International; 06/2010
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    ABSTRACT: Abnormal Gm degradation and GIDL current in the Uniform Channel Program and Erase (UCPE) floating gate 2 transistor (2T)-embedded flash cell (eFlash) is investigated. Severe charge trapping and de-trapping at the floating gate to junction overlap area lead to the endurance failure and cell current degradation. Control Gate (CG)-Select Gate (SG) Inter-junction trapping further degrades endurance and GIDL due to enhanced field and deeply depleted inter-junction. High temperature retention bake showed the charge relaxation and subsequent failure in the programmed cells. In this paper, we report both Gm and GIDL improvement of 2T eFlash memory with optimized gate-sidewall and extra thermal steps within the constraint of embedding flash process in the 65 nm standard logic process.
    Non-Volatile Memory Technology Symposium (NVMTS), 2009 10th Annual; 11/2009
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    ABSTRACT: Via electromigration (EM) lifetime correlates with the initial via resistance. We have found that the single Kelvin via structure is more effective as a wafer-level reliability (WLR) monitor than the via chains. Using this monitor, we have optimized the via process for 0.35 u/0.25 u applications
    Integrated Reliability Workshop Final Report, 1998. IEEE International; 11/1998
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    ABSTRACT: The reliability of a new amorphous silicon/dielectric antifuse is characterized and modeled. Unprogrammed antifuse leakage and time-to-breakdown are functions not only of applied voltage but also of stressing polarity and temperature. Both breakdown and leakage criteria are used to investigate their effects on time-to-fail. A thermal model incorporates the effects of programming and stress currents, ambient temperature, and variation of antifuse resistance with temperature. The measured temperature dependence of antifuse resistance is used for the first time to derive key physical parameters in the model
    Reliability Physics Symposium, 1997. 35th Annual Proceedings., IEEE International; 05/1997
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    ABSTRACT: Antifuse structure as a programming element has become increasingly popular in field programmable gate array devices. In this paper we discuss the characteristics of various antifuse structures. Tradeoffs between performance and reliability are also discussed
    Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International; 01/1993
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    ABSTRACT: The total dose effects and SEEs of RT54SX, a new radiation tolerant antifuse FPGA family, are presented. This device family employs a metal-to-metal antifuse technology and a sea-of-modules architecture. Devices manufactured by both 0.6 µm and 0.25 µm technology levels are tested. The devices demonstrate the total dose tolerance better than 100 krad(Si). They are SEL and SEDR immune. For SEU, 0.6 µm has LETth of 12 MeV-cm 2 /mg and cross section of 2 x 10-6 cm2, and 0.25 µm has a lower LETth but approximately the same cross section. Total dose hardening and SEU hardening are also investigated. I. RT54SX