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ABSTRACT: This work demonstrates the feasibility of a polycrystalline silicon thin-film transistor (poly-Si TFTs) nonvolatile memory (NVM) that utilizes a Pi-shaped gate (Pi-gate) and multiple nanowire channels with a HfO<sub>2</sub> charge-trapping layer. The TFT NVM with the Pi-gate nanowires (NWs) structure has a higher program/erase (P/E) efficiency than that of the conventional single-channel TFT NVM; the memory window can achieve 2.3 V, only needs a programming time of 1 μs. This high P/E efficiency follows from the improved gate control of the Pi-gate structure. A Pi-gate NWs poly-Si TFT NVM with a Si<sub>3</sub>N<sub>4</sub> charge-trapping layer was also fabricated. Since HfO<sub>2</sub> has a deeper conduction band than Si<sub>3</sub>N<sub>4</sub>, the device with the HfO<sub>2</sub> charge-trapping layer has a higher programming efficiency and the better retention characteristics than that with the Si<sub>3</sub>N<sub>4</sub> charge-trapping layer. Additionally, the high programming efficiency allows the device with the HfO<sub>2</sub> charge-trapping layer to undergo more P/E cycles than that with the Si<sub>3</sub> N<sub>4</sub> charge-trapping layer.
IEEE Transactions on Nanotechnology 04/2011; · 2.29 Impact Factor
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ABSTRACT: This letter demonstrates a novel twin poly-Si thin-film transistor (TFT) electrical erasable PROM (EEPROM) that utilizes trigate nanowires (NWs). The NW TFT EEPROM has superior gate control because its trigate structure provides a higher memory window and program/erase (P/E) efficiency over those of a single-channel one. For endurance and retention, the memory window can be maintained at 1.5 V after 10<sup>3</sup> P/E cycles and 25% charge loss for ten years of NW twin poly-Si EEPROM. This investigation explores its feasibility in future active matrix liquid crystal display system-on-panel and 3-D stacked Flash memory applications.
IEEE Electron Device Letters 12/2008; · 2.85 Impact Factor
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ABSTRACT: This work studies the two-bit effect of trigate nanowires polycrystalline silicon thin-film transistors with silicon-oxide-nitride-oxide-silicon nonvolatile memory. The two-bit effect is clearly demonstrated by the localized charge trapping in a nitride layer. The programing operation is performed by channel hot electrons injection, and erasing is performed by channel hot holes injection. The threshold voltage shifts between forward read and reverse read schemes is 2.2 V . At a large gate length of 5 μ m , the programing is dominated by Fowler–Nordheim tunneling, resulting in the absence of two-bit storage capacity. Regarding the two-bit programing and erasing speed characteristics, one-bit programing or erasing does not affect the other bit.
Applied Physics Letters 05/2008; · 3.84 Impact Factor
