H.M. Teixeira

University of Aveiro, Aveiro, Aveiro, Portugal

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Publications (11)5.99 Total impact

  • H.M. Teixeira, T.R. Cunha, J.C. Pedro
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    ABSTRACT: The advent of the software-defined-radio (SDR) concept, has placed many of the traditional analog functions of RF wireless transceivers in the digital domain, attracting an increased interest of the RF community to the characterization and modeling of digital and mixed-mode circuits such as analog-to-digital converters, digital-to-analog converters and input/output digital buffers/drivers. Therefore, this paper presents an experimental procedure to characterize high speed packaged digital buffers under large signal regime. Based on an inexpensive RF broadband bi-directional coupler, the dynamic behavior of the Pull-Down/Pull-Up networks is determined. The test fixture effects are removed through a well-defined de-embedding procedure, allowing the determination of the voltage/current at the buffer's output. The paper also addresses the buffer's characterization under switching conditions.
    Microwave Conference (EuMC), 2013 European; 01/2013
  • H.M. Teixeira, W. Dghais, T.R. Cunha, J.C. Pedro
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    ABSTRACT: This paper presents a measurement setup for digital output buffers' characterization. This is of recognized importance for the integrated circuit industry and has rarely been addressed in the literature related to output buffer modeling. Currently, the model extraction is typically performed by simulating the transistor-level model of the device, which raises important issues regarding intellectual property protection, long-simulation times, and deembedding inaccuracies of the high-speed device mount parasitics. In the presented approach, a well-defined experimental procedure is proposed to extract and validate a state-of-the-art model for a commercial noninverting output buffer in a packaged format.
    IEEE Transactions on Instrumentation and Measurement 01/2013; 62(7):1892-1899. · 1.36 Impact Factor
  • W. Dghais, H.M. Teixeira, T.R. Cunha, J.C. Pedro
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    ABSTRACT: An efficient and accurate table-based behavioral model extraction for high-speed input/output (I/O) buffer behavior is presented in this paper. The nonlinear current-voltage (I-V) and charge-voltage (Q-V) functions describing the graybox model structure are extracted via least-squares methods using identification signals recorded from large signal transient simulation. The resulting continuous time-domain model is easily implemented as lookup table and leads to an increase in modeling accuracy, and a decrease in computation time, as is demonstrated in this paper. Finally, its application in a realistic signal integrity scenario is presented, demonstrating a superior performance compared to that of the I/O buffer information specification model.
    IEEE Transactions on Components, Packaging, and Manufacturing Technology 01/2013; 3(3):500-507. · 1.26 Impact Factor
  • W. Dghais, H.M. Teixeira, T.R. Cunha, J.C. Pedro
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    ABSTRACT: This paper presents a computational efficient table-based behavioral model implementation for transient simulation of high-speed digital I/O buffers. The proposed model is non-recursive and its formulation is supported by the analysis of the driver's physical constitution.
    Signal and Power Integrity (SPI), 2012 IEEE 16th Workshop on; 01/2012
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    ABSTRACT: This paper addresses the generation of behavioral models of digital integrated circuits (ICs) for signal and power integrity simulations. The proposed models are obtained by external measurements carried out at the device ports only and by the combined application of specialized state-of-the-art modeling techniques. The present approach exploits a behavioral formulation, leading to models reproducing all the behavior of the IC ports as the input/output buffers and the core power delivery network. The modeling procedure is demonstrated for a commercial nor Flash memory in 90-nm technology housed by a specifically designed test fixture.
    IEEE Transactions on Instrumentation and Measurement 11/2011; · 1.36 Impact Factor
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    ABSTRACT: The growing importance of signal integrity (SI) analysis in integrated circuits (ICs), revealed by modern system-in-package methods, is demanding for new models for the IC sub-systems which are both accurate, efficient and extractable by simple measurement procedures. This paper presents the contribution for the establishment of an integrated IC modeling approach whose performance is assessed by direct comparison with the signals measured in laboratory of two distinct memory IC devices. Based on the identification of the main blocks of a typical IC device, the modeling approach consists of a network of system-level sub-models, some of which with already demonstrated accuracy, which simulated the IC interfacing behavior. Emphasis is given to the procedures that were developed to validate by means of laboratory measurements (and not by comparison with circuit-level simulations) the model performance, which is a novel and important aspect that should be considered in the design of IC models that are useful for SI analysis.
    IEEE Transactions on Components, Packaging, and Manufacturing Technology 09/2011; · 1.26 Impact Factor
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    IEEE T. Instrumentation and Measurement. 01/2011; 60:3471-3479.
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    ABSTRACT: The RF power amplifier (PA) is a nonlinear system with an intrinsic and dynamic feedback mechanism. The application of an adequate linearizer (which is also a nonlinear dynamic system) inserted at the input of the signal path (i.e., predistortion) is very important to maintain a linear transmission chain when the PA carries high power signals (avoiding spectral regrowth). This article presents a new PA linearizer model whose topology has support on the physical behavior of the general PA electronic circuit. As the proposed model is of a feed-forward nature, it is suited for implementation on digital hardware devices, such as field programmable gate array and digital signal processor. Validation tests were performed on the linearization of a 900 MHz PA excited with WCDMA-3GPP signals. Comparison with other state-of-the-art linearizer models is included, demonstrating very good linearization results. Moreover, this model has potential to be an adequate linearizer for a wider range of applications since it has physical support. © 2010 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2010.
    International Journal of RF and Microwave Computer-Aided Engineering 02/2010; 20(3):321 - 332. · 0.75 Impact Factor
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    ABSTRACT: This paper presents a new power amplifier (PA) linearizer model whose topology has support on the physical recursive behavior of the general PA electronic circuit. The resulting model presents a topology that, in its essence, is non recursive, which makes it suited for an easy implementation on digital hardware devices (such as FPGAs and DSPs). Validation tests were performed on a 900 MHz PA excited with WCDMA-3GPP signals and comparison with other linearizer models demonstrated its excellence. Due to its support on the PA physical behavior, the proposed predistorter model has the potential to be an adequate linearizer for a wide range of PA device technologies and excitation signals.
    01/2010;
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    ABSTRACT: This paper proves that the traditional way of deriving power amplifier low-pass equivalent complex-signal Volterra models from their original band-pass RF real-signal Volterra models is too restrictive, and so does not lead to an optimal model. Then, it proposes a much richer alternative approach. Instead of deriving the base-band Volterra model from the RF Volterra model, we started by a general Volterra series expansion of a complex-signal to only then impose the restrictions of odd parity required by the low-pass equivalent polynomial approximation. This way, not only we prove that the theoretical reticence that was raised to similar approaches previously proposed for the memoryless polynomial and the memory polynomial were unfounded, as experimental results fully justified this novel approach.
    Microwave Symposium Digest, 2009. MTT '09. IEEE MTT-S International; 07/2009
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    ABSTRACT: This paper focuses on the power delivery characterization of high-speed IC memories by means of on-chip measurements. A systematic analysis of the measurement setup, of the effects of chip biasing and of the use of the measured responses to develop models defined by simplified circuit equivalents is given. All the results collected in the paper are based on real measurements carried out on a commercial 90 nm flash memory.
    Signal Propagation on Interconnects, 2009. SPI '09. IEEE Workshop on; 06/2009